IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2015-12-03 11:15
Logic Design of A Single-Flux-Quantum Microprocessor
Koki Ishida, Tomonori Tsuhata (Kyushu Univ.), Masamitsu Tanaka (Nagoya Univ.), Takatsugu Ono, Koji Inoue (Kyushu Univ.) CPSY2015-73
Abstract (in Japanese) (See Japanese page) 
(in English) CMOS microprocessors have been facing a limitation for clock speed improvement because of increasing
computing power. Using SFQ (Single-Flux-Quantum) devices and circuits is a promising way to solve the power wall problem. In a previous study, we have suggested proper archtecture to design SFQ microprocessor. This
paper designs an SFQ microprocessor and assesses in terms of clock frequencies, area, and power consumption.
The evaluation results show that an SFQ microprocessor clock speed passed 222Ghz and 56 times faster than
CMOS microprocessor. Moreover, the SFQ microprocessor consumes only 1/5000 of energy compared to CMOS
Keyword (in Japanese) (See Japanese page) 
(in English) Microprocessor / Single-Flux-Quantum Circuit / High Performance / Low Power / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 342, CPSY2015-73, pp. 69-74, Dec. 2015.
Paper # CPSY2015-73 
Date of Issue 2015-11-24 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2015-73

Conference Information
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Logic Design of A Single-Flux-Quantum Microprocessor 
Sub Title (in English)  
Keyword(1) Microprocessor  
Keyword(2) Single-Flux-Quantum Circuit  
Keyword(3) High Performance  
Keyword(4) Low Power  
1st Author's Name Koki Ishida  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
2nd Author's Name Tomonori Tsuhata  
2nd Author's Affiliation Kyushu University (Kyushu Univ.)
3rd Author's Name Masamitsu Tanaka  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
4th Author's Name Takatsugu Ono  
4th Author's Affiliation Kyushu University (Kyushu Univ.)
5th Author's Name Koji Inoue  
5th Author's Affiliation Kyushu University (Kyushu Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2015-12-03 11:15:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2015-73 
Volume (vol) vol.115 
Number (no) no.342 
Page pp.69-74 
Date of Issue 2015-11-24 (CPSY) 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan