Paper Abstract and Keywords |
Presentation |
2015-12-03 14:10
Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-68 DC2015-64 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In synchronous circuits, peak currents flow at a constant frequency since a global clock signal which is a timing signal activates storage elements in the whole chip. Electromagnetic waves with the constant frequency may occur in synchronous circuits due to the peak currents. As a result, several noises occur. As a circuit size increases, the influence of the noises becomes remarkable since peak currents increase. On the other hand, in asynchronous circuits, peak currents are flattened since timing signals perform based on the request-and-acknowledge handshaking protocol only when and where they are needed between registers. In this research, we implemented some asynchronous bandpass filter circuits using 130nm process technology which can reduce peak currents, instead of synchronous circuits which are commonly used now. Then, their performances including the noise characteristics are compared with those of synchronous bandpass filter circuits. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Dependable Technology / Asynchronous Circuit / Filter Circuit / MOUSETRAP Circuit / HSPICE / Verilog / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 338, VLD2015-68, pp. 195-200, Dec. 2015. |
Paper # |
VLD2015-68 |
Date of Issue |
2015-11-24 (VLD, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2015-68 DC2015-64 |
Conference Information |
Committee |
VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
Conference Date |
2015-12-01 - 2015-12-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Gaia 2015 -New Field of VLSI Design- |
Paper Information |
Registration To |
VLD |
Conference Code |
2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits |
Sub Title (in English) |
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Keyword(1) |
Dependable Technology |
Keyword(2) |
Asynchronous Circuit |
Keyword(3) |
Filter Circuit |
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MOUSETRAP Circuit |
Keyword(5) |
HSPICE |
Keyword(6) |
Verilog |
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Keyword(8) |
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1st Author's Name |
Tatsuya Ishikawa |
1st Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
2nd Author's Name |
Atsushi Kurokawa |
2nd Author's Affiliation |
Hirosaki University (Hirosaki Univ.) |
3rd Author's Name |
Masashi Imai |
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Hirosaki University (Hirosaki Univ.) |
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Speaker |
Author-1 |
Date Time |
2015-12-03 14:10:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2015-68, DC2015-64 |
Volume (vol) |
vol.115 |
Number (no) |
no.338(VLD), no.339(DC) |
Page |
pp.195-200 |
#Pages |
6 |
Date of Issue |
2015-11-24 (VLD, DC) |
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