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Paper Abstract and Keywords
Presentation 2015-12-03 14:10
An approach to LFSR/MISR seed generation for delay fault BIST
Daichi Shimazu, Satishi Ohtake (Oita Univ.) VLD2015-70 DC2015-66
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a method of LFSR/MISR seed generation for delay fault BIST.
A widely used conventional way to generate seeds is the following: a test cube for a fault is first generated and the cube is then converted into a seed.
However, the conversion does not always succeed and the fault may not be detected.
The authors' group has proposed an LFSR seed generation method for scan based BIST which aims to detect delay faults using ATPG with the launch-off-capture (LoC) scheme.
This approach models dependency between an LFSR seed and the value of scan FFs in a combinational circuit called an XOR network and connects it to the CUT as a constraint of ATPG.
The model enables direct seed generation by using ATPG.
In this paper, an XOR network supporting LFSR and MISR for delay fault testing is designed and used for direct seed generation.
Experiments using ITC'99 and IWLS'05 benchmark circuits are performed to evaluate the effectiveness of the proposed method.
Keyword (in Japanese) (See Japanese page) 
(in English) BIST / seed generation / LFSR/MISR / delay fault / constrained test generation / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 339, DC2015-66, pp. 213-218, Dec. 2015.
Paper # DC2015-66 
Date of Issue 2015-11-24 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2015-70 DC2015-66

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2015-12-01 - 2015-12-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagasaki Kinro Fukushi Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2015 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An approach to LFSR/MISR seed generation for delay fault BIST 
Sub Title (in English)  
Keyword(1) BIST  
Keyword(2) seed generation  
Keyword(3) LFSR/MISR  
Keyword(4) delay fault  
Keyword(5) constrained test generation  
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1st Author's Name Daichi Shimazu  
1st Author's Affiliation Oita University (Oita Univ.)
2nd Author's Name Satishi Ohtake  
2nd Author's Affiliation Oita University (Oita Univ.)
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Speaker Author-1 
Date Time 2015-12-03 14:10:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2015-70, DC2015-66 
Volume (vol) vol.115 
Number (no) no.338(VLD), no.339(DC) 
Page pp.213-218 
#Pages 6 
Date of Issue 2015-11-24 (VLD, DC) 

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