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Paper Abstract and Keywords
Presentation 2015-12-14 16:00
Operation verification of neural network using a simplified element by FPGA
Nao Nakamura, Ryuhei Morita, Yuki Koga, Hiroki Nakanishi, Sumio Sugisaki, Tomoharu Yokoyama, Koki Watada, Tokiyoshi Matsuda, Mutsumi Kimura (Ryukoku Univ.) EID2015-23 SDM2015-106
Abstract (in Japanese) (See Japanese page) 
(in English) Neural networks are those that aim to realize advanced information processing functions of the brain and nervous system of a living body. We are developing neural networks using thin-film transistors. To ensure the large number of neurons, it is essential to develop a simplified neurons. Therefore, we prepared three types of neuron circuits and verified the operation by FPGA. As a result, we succeeded in operating all circuits properly.
Keyword (in Japanese) (See Japanese page) 
(in English) Neural Network / Simplified Element / FPGA / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 362, EID2015-23, pp. 61-64, Dec. 2015.
Paper # EID2015-23 
Date of Issue 2015-12-07 (EID, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF EID2015-23 SDM2015-106

Conference Information
Committee EID SDM  
Conference Date 2015-12-14 - 2015-12-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Ryukoku University, Avanti Kyoto Hall 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Si and Si-related Materials and Devices, and Display Technology 
Paper Information
Registration To EID 
Conference Code 2015-12-EID-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Operation verification of neural network using a simplified element by FPGA 
Sub Title (in English)  
Keyword(1) Neural Network  
Keyword(2) Simplified Element  
Keyword(3) FPGA  
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1st Author's Name Nao Nakamura  
1st Author's Affiliation Ryukoku University (Ryukoku Univ.)
2nd Author's Name Ryuhei Morita  
2nd Author's Affiliation Ryukoku University (Ryukoku Univ.)
3rd Author's Name Yuki Koga  
3rd Author's Affiliation Ryukoku University (Ryukoku Univ.)
4th Author's Name Hiroki Nakanishi  
4th Author's Affiliation Ryukoku University (Ryukoku Univ.)
5th Author's Name Sumio Sugisaki  
5th Author's Affiliation Ryukoku University (Ryukoku Univ.)
6th Author's Name Tomoharu Yokoyama  
6th Author's Affiliation Ryukoku University (Ryukoku Univ.)
7th Author's Name Koki Watada  
7th Author's Affiliation Ryukoku University (Ryukoku Univ.)
8th Author's Name Tokiyoshi Matsuda  
8th Author's Affiliation Ryukoku University (Ryukoku Univ.)
9th Author's Name Mutsumi Kimura  
9th Author's Affiliation Ryukoku University (Ryukoku Univ.)
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Speaker Author-1 
Date Time 2015-12-14 16:00:00 
Presentation Time 15 minutes 
Registration for EID 
Paper # EID2015-23, SDM2015-106 
Volume (vol) vol.115 
Number (no) no.362(EID), no.363(SDM) 
Page pp.61-64 
#Pages 4 
Date of Issue 2015-12-07 (EID, SDM) 

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