Paper Abstract and Keywords |
Presentation |
2015-12-14 16:00
Operation verification of neural network using a simplified element by FPGA Nao Nakamura, Ryuhei Morita, Yuki Koga, Hiroki Nakanishi, Sumio Sugisaki, Tomoharu Yokoyama, Koki Watada, Tokiyoshi Matsuda, Mutsumi Kimura (Ryukoku Univ.) EID2015-23 SDM2015-106 Link to ES Tech. Rep. Archives: EID2015-23 SDM2015-106 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Neural networks are those that aim to realize advanced information processing functions of the brain and nervous system of a living body. We are developing neural networks using thin-film transistors. To ensure the large number of neurons, it is essential to develop a simplified neurons. Therefore, we prepared three types of neuron circuits and verified the operation by FPGA. As a result, we succeeded in operating all circuits properly. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Neural Network / Simplified Element / FPGA / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 362, EID2015-23, pp. 61-64, Dec. 2015. |
Paper # |
EID2015-23 |
Date of Issue |
2015-12-07 (EID, SDM) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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EID2015-23 SDM2015-106 Link to ES Tech. Rep. Archives: EID2015-23 SDM2015-106 |
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