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Paper Abstract and Keywords
Presentation 2015-12-17 10:40
Improvement of TLB performance of MIPS-based processor
Gun Muto, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo (Mie Univ.) ICD2015-65 CPSY2015-78
Abstract (in Japanese) (See Japanese page) 
(in English) TLB is onw of the important modules to enhance memory access performance. Generally, increasing the number of TLB entries contributes TLB hit rate and performance improvement. However, MIPS32 ISA limits the number of TLB entries to 64. This paper proposes mechanism to increase TLB entries without breaking binary compatibility. Our approach analyzes executing code related to TLB access dynamically, and behaves like 64-entry TLB. According to our simulation results, our approach can improve TLB hit rate without breaking binary compatibility.
Keyword (in Japanese) (See Japanese page) 
(in English) TLB / MIPS / high performance / embedded processor / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 374, CPSY2015-78, pp. 13-18, Dec. 2015.
Paper # CPSY2015-78 
Date of Issue 2015-12-10 (ICD, CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2015-65 CPSY2015-78

Conference Information
Committee ICD CPSY  
Conference Date 2015-12-17 - 2015-12-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyoto Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2015-12-ICD-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Improvement of TLB performance of MIPS-based processor 
Sub Title (in English)  
Keyword(1) TLB  
Keyword(2) MIPS  
Keyword(3) high performance  
Keyword(4) embedded processor  
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1st Author's Name Gun Muto  
1st Author's Affiliation Mie University (Mie Univ.)
2nd Author's Name Takahiro Sasaki  
2nd Author's Affiliation Mie University (Mie Univ.)
3rd Author's Name Yuki Fukazawa  
3rd Author's Affiliation Mie University (Mie Univ.)
4th Author's Name Toshio Kondo  
4th Author's Affiliation Mie University (Mie Univ.)
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Speaker Author-1 
Date Time 2015-12-17 10:40:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # ICD2015-65, CPSY2015-78 
Volume (vol) vol.115 
Number (no) no.373(ICD), no.374(CPSY) 
Page pp.13-18 
#Pages 6 
Date of Issue 2015-12-10 (ICD, CPSY) 

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