Paper Abstract and Keywords |
Presentation |
2015-12-18 09:00
Evaluation of Soft Error Tolerance of Redundant Flip-Flop in 65nm Bulk and FD-SOI Processes. Eiji Sonezaki, Kubota Kanto, Masaki Masuda, Shohei Kanda, Jun Furuta, Kazutoshi Kobayashi (KIT) ICD2015-83 CPSY2015-96 Link to ES Tech. Rep. Archives: ICD2015-83 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
According to process down scaling, LSI becomes less reliable for soft errors. To increase the tolerance of FFs for soft errors, several redundant FF structures are proposed such as the TMR FF. However, the
redundant FF has large area and power consumption overhead. Although it is very hard to reduce the area overhead, the power consumption overhead can be reduced to adapt low power consumption techniques. We
proposed a low power consumption redundant FFs (BCDMRACFF, DICEACFF) by combining conventional redundant FFs (BCDMRFF, DICEFF) and low power consumption techniques. We evaluated tolerance for soft error of proposed FFs in 65nm Bulk and Thin BOX FD-SOI. In Bulk, tolerance of BCDMRACFF and DICEACFF have 20 and 17 times higher than TGFF, respectively. In Thin BOX FD-SOI, number of error in proposed FFs is only one. Thin BOX FD-SOI + BCDMR or DICE have very high tolerance for soft error. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Soft error / BCDMR / redundant FF / heavy Ion / low power consumption / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 373, ICD2015-83, pp. 69-74, Dec. 2015. |
Paper # |
ICD2015-83 |
Date of Issue |
2015-12-10 (ICD, CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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ICD2015-83 CPSY2015-96 Link to ES Tech. Rep. Archives: ICD2015-83 |
Conference Information |
Committee |
ICD CPSY |
Conference Date |
2015-12-17 - 2015-12-18 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kyoto Institute of Technology |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2015-12-ICD-CPSY |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Evaluation of Soft Error Tolerance of Redundant Flip-Flop in 65nm Bulk and FD-SOI Processes. |
Sub Title (in English) |
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Keyword(1) |
Soft error |
Keyword(2) |
BCDMR |
Keyword(3) |
redundant FF |
Keyword(4) |
heavy Ion |
Keyword(5) |
low power consumption |
Keyword(6) |
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Keyword(7) |
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Keyword(8) |
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1st Author's Name |
Eiji Sonezaki |
1st Author's Affiliation |
Kyoto Institute of Technology (KIT) |
2nd Author's Name |
Kubota Kanto |
2nd Author's Affiliation |
Kyoto Institute of Technology (KIT) |
3rd Author's Name |
Masaki Masuda |
3rd Author's Affiliation |
Kyoto Institute of Technology (KIT) |
4th Author's Name |
Shohei Kanda |
4th Author's Affiliation |
Kyoto Institute of Technology (KIT) |
5th Author's Name |
Jun Furuta |
5th Author's Affiliation |
Kyoto Institute of Technology (KIT) |
6th Author's Name |
Kazutoshi Kobayashi |
6th Author's Affiliation |
Kyoto Institute of Technology (KIT) |
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Speaker |
Author-1 |
Date Time |
2015-12-18 09:00:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2015-83, CPSY2015-96 |
Volume (vol) |
vol.115 |
Number (no) |
no.373(ICD), no.374(CPSY) |
Page |
pp.69-74 |
#Pages |
6 |
Date of Issue |
2015-12-10 (ICD, CPSY) |
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