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Paper Abstract and Keywords
Presentation 2016-01-20 14:40
FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler
Kohei Nagasu, Kentaro Sano (Tohoku Univ.), Fumiya Kono, Naohito Nakasato (The Univ. of Aizu) VLD2015-92 CPSY2015-124 RECONF2015-74
Abstract (in Japanese) (See Japanese page) 
(in English) Method of Splitting Tsunami (MOST) is a numerical solver of Shallow Water Equations (SWEs), which is used for forecasting tsunami. Tsunami Simulation using MOST is usually run with a supercomputer, however it is difficult to take a rapid responce to disaster with such a large-scale computing system. One of the solutions to this problem is development of a compact system with custom computing machines. In this paper, we use Field-Programmable Gate Arrays (FPGAs) as a platform to build a custom computing machine of Tsunami simulation based on MOST. We design Stream Processing Element (SPE) as a hardware SWEs solver by using our stream-computation hardware compiler, called SPGen. We implement hardware with a single SPE or two cascaded SPEs on 28nm ALTERA Stratix V FPGA, which achieves 51.8GFlop/s or 103.7GFlop/s, bringing the performance per power of 1.71GFlop/sW or 2.91GFlop/sW, respectively.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGAs / stream-computation / shallow water equations / method of splitting tsunami / tsunami simulator / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 400, RECONF2015-74, pp. 131-136, Jan. 2016.
Paper # RECONF2015-74 
Date of Issue 2016-01-12 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2015-92 CPSY2015-124 RECONF2015-74

Conference Information
Conference Date 2016-01-19 - 2016-01-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2016-01-VLD-CPSY-RECONF-SLDM-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler 
Sub Title (in English)  
Keyword(1) FPGAs  
Keyword(2) stream-computation  
Keyword(3) shallow water equations  
Keyword(4) method of splitting tsunami  
Keyword(5) tsunami simulator  
1st Author's Name Kohei Nagasu  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Kentaro Sano  
2nd Author's Affiliation Tohoku University (Tohoku Univ.)
3rd Author's Name Fumiya Kono  
3rd Author's Affiliation The University of Aizu (The Univ. of Aizu)
4th Author's Name Naohito Nakasato  
4th Author's Affiliation The University of Aizu (The Univ. of Aizu)
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Speaker Author-1 
Date Time 2016-01-20 14:40:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2015-92, CPSY2015-124, RECONF2015-74 
Volume (vol) vol.115 
Number (no) no.398(VLD), no.399(CPSY), no.400(RECONF) 
Page pp.131-136 
Date of Issue 2016-01-12 (VLD, CPSY, RECONF) 

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