Paper Abstract and Keywords |
Presentation |
2016-01-21 13:25
A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algorithm can be applied to static delay variations by switching the pre-defined behavior scenarios before the circuit starts to operate. The proposed algorithm can be applied to dynamic delay variations if we can effectively embed timing-violation prediction scheme. In this paper, we propose a floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations. In our algorithm, we adopt distributed register/controller architectures to incorporate floorplanning into high-level synthesis efficiently. Moreover, we discuss timing-violation prediction schemes for switching behavior scenarios. Particularly, we focus on critical path replica and timing-error predictable flip-flops. Experimental results demonstrate the efficiency of our proposed timing-violation prediction schemes, which can reduce the average latency by up to 25.0% compared to the previous methods. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
high-level synthesis / distributed register/controller architecture / dynamic delay variation / timing violation prediction / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 115, no. 398, VLD2015-105, pp. 209-214, Jan. 2016. |
Paper # |
VLD2015-105 |
Date of Issue |
2016-01-12 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2015-105 CPSY2015-137 RECONF2015-87 |
Conference Information |
Committee |
VLD CPSY RECONF IPSJ-SLDM IPSJ-ARC |
Conference Date |
2016-01-19 - 2016-01-21 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2016-01-VLD-CPSY-RECONF-SLDM-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations |
Sub Title (in English) |
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Keyword(1) |
high-level synthesis |
Keyword(2) |
distributed register/controller architecture |
Keyword(3) |
dynamic delay variation |
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timing violation prediction |
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1st Author's Name |
Koki Igawa |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Masao Yanagisawa |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Nozomu Togawa |
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Waseda University (Waseda Univ.) |
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Speaker |
Author-1 |
Date Time |
2016-01-21 13:25:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2015-105, CPSY2015-137, RECONF2015-87 |
Volume (vol) |
vol.115 |
Number (no) |
no.398(VLD), no.399(CPSY), no.400(RECONF) |
Page |
pp.209-214 |
#Pages |
6 |
Date of Issue |
2016-01-12 (VLD, CPSY, RECONF) |
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