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Paper Abstract and Keywords
Presentation 2016-01-21 09:55
Improvement of operational stability of SFQ logic gate with optimized Josephson comparator
Kenta Asakura, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Nat Univ.) SCE2015-37
Abstract (in Japanese) (See Japanese page) 
(in English) A single-flux-quantum (SFQ) circuits has been studied because of its low power and high-speed operation. Because the bit energy of the SFQ circuit is extremely low, careful design is required to build reliable large-scale SFQ circuit that has the ultra-low error rate. In this study, we investigated improvement of a bit-error rate of the SFQ logic gate by optimizing Josephson comparators, which is a pair of serially connected Josephson junctions and make decisions of the signal outputs, in the logic gate. We have investigated the bit error rate of SFQ logic gates that have various circuit parameters and structures. Measurements result show that the bit-error rate can be improved by optimizing SFQ OR gate. The difference is 3% at the bit-error rate of 10-4.
Keyword (in Japanese) (See Japanese page) 
(in English) SFQ / comparator / logic gate / gray zone width / bit-error rate / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 412, SCE2015-37, pp. 7-10, Jan. 2016.
Paper # SCE2015-37 
Date of Issue 2016-01-14 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2015-37

Conference Information
Committee SCE  
Conference Date 2016-01-21 - 2016-01-21 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SCE 
Conference Code 2016-01-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Improvement of operational stability of SFQ logic gate with optimized Josephson comparator 
Sub Title (in English)  
Keyword(1) SFQ  
Keyword(2) comparator  
Keyword(3) logic gate  
Keyword(4) gray zone width  
Keyword(5) bit-error rate  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Kenta Asakura  
1st Author's Affiliation Yokohama National University (Yokohama Nat Univ.)
2nd Author's Name Yuki Yamanashi  
2nd Author's Affiliation Yokohama National University (Yokohama Nat Univ.)
3rd Author's Name Nobuyuki Yoshikawa  
3rd Author's Affiliation Yokohama National University (Yokohama Nat Univ.)
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Speaker Author-1 
Date Time 2016-01-21 09:55:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2015-37 
Volume (vol) vol.115 
Number (no) no.412 
Page pp.7-10 
#Pages 4 
Date of Issue 2016-01-14 (SCE) 

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