IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2016-01-29 11:45
Fault tolerance of paralleled boost converters with WTA switching
Shouta Hakamada, Yasuo Murata, Toshimichi Saito (HU) NLP2015-140
Abstract (in Japanese) (See Japanese page) 
(in English) This paper studies a paralleled system of boost converters with WTA-based switching rule.
The system exhibits multi-phase synchronization phenomena and chaotic phenomena.
The multi-phase synchronization is suitable for ripple reduction, current sharing,
and efficient power supply.
The WTA-based switching rule is effective to reinforce the fault tolerance.
Simplifying the system into a piecewise linear model and applying the mapping procedure,
stability of the synchronization phenomena and ripple waveforms can be analyzed precisely.
Presenting a simple test circuit, typical phenomena can be confirmed experimentally.
Keyword (in Japanese) (See Japanese page) 
(in English) paralleled power converters / multi-phase synchronization / chaos / ripple reduction / fault tolerance / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 425, NLP2015-140, pp. 81-86, Jan. 2016.
Paper # NLP2015-140 
Date of Issue 2016-01-21 (NLP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF NLP2015-140

Conference Information
Committee NC NLP  
Conference Date 2016-01-28 - 2016-01-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Implementation of Neuro Computing,Analysis and Modeling of Human Science, etc 
Paper Information
Registration To NLP 
Conference Code 2016-01-NC-NLP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fault tolerance of paralleled boost converters with WTA switching 
Sub Title (in English)  
Keyword(1) paralleled power converters  
Keyword(2) multi-phase synchronization  
Keyword(3) chaos  
Keyword(4) ripple reduction  
Keyword(5) fault tolerance  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shouta Hakamada  
1st Author's Affiliation Hosei University (HU)
2nd Author's Name Yasuo Murata  
2nd Author's Affiliation Hosei University (HU)
3rd Author's Name Toshimichi Saito  
3rd Author's Affiliation Hosei University (HU)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2016-01-29 11:45:00 
Presentation Time 25 minutes 
Registration for NLP 
Paper # NLP2015-140 
Volume (vol) vol.115 
Number (no) no.425 
Page pp.81-86 
#Pages
Date of Issue 2016-01-21 (NLP) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan