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Paper Abstract and Keywords
Presentation 2016-03-02 13:50
Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection
Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Tech) VLD2015-140
Abstract (in Japanese) (See Japanese page) 
(in English) General synchronous circuits are proposed as having taken the place of complete synchronous circuits and do not necessarily require simultaneity of the clock distribution to every flip-flop. They run lower clock period than the maximum delay between flip-flops and enable the reduction of minimum clock period by delay insertion. However, there is a theoretical lower bound of clock period that can be achieved by delay insertion to general synchronous circuits, called the maximum delay-to-register ratio. In this paper, we propose an acceleration method of general synchronous circuits using variable latency technique through realizing clock period that is exceeded the lower limit. Various latency circuits' effective performance depends on its clock period and the frequency of timing-errors detected dynamically. Thus, in proposed method, we use delay insertion in addition to various latency technique, and we reduce minimum clock period while inhibiting timing-errors. We evaluate MIPS I compatible processors with applying the proposed method, using gate-level simulation. Evaluation result shows that by applying the proposed method, general synchronous circuits significantly improve performance with small circuit area overhead.
Keyword (in Japanese) (See Japanese page) 
(in English) general synchronous circuit / delay insertion / various latency / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 465, VLD2015-140, pp. 167-172, Feb. 2016.
Paper # VLD2015-140 
Date of Issue 2016-02-22 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2015-140

Conference Information
Committee VLD  
Conference Date 2016-02-29 - 2016-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2016-02-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection 
Sub Title (in English)  
Keyword(1) general synchronous circuit  
Keyword(2) delay insertion  
Keyword(3) various latency  
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1st Author's Name Hiroshi Nakatsuka  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Atsushi Takahashi  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2016-03-02 13:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2015-140 
Volume (vol) vol.115 
Number (no) no.465 
Page pp.167-172 
#Pages 6 
Date of Issue 2016-02-22 (VLD) 

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