Paper Abstract and Keywords |
Presentation |
2016-04-14 11:00
[Invited Lecture]
A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi (Kobe Univ.), Koji Nii (Renesas Electronics), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2016-3 Link to ES Tech. Rep. Archives: ICD2016-3 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Image Memory / Multiport SRAM / 8T / FD-SOI / 28-nm / Majority Logic / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 3, ICD2016-3, pp. 13-16, April 2016. |
Paper # |
ICD2016-3 |
Date of Issue |
2016-04-07 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2016-3 Link to ES Tech. Rep. Archives: ICD2016-3 |