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Paper Abstract and Keywords
Presentation 2016-04-14 11:00
[Invited Lecture] A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor
Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi (Kobe Univ.), Koji Nii (Renesas Electronics), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2016-3
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM.
Keyword (in Japanese) (See Japanese page) 
(in English) Image Memory / Multiport SRAM / 8T / FD-SOI / 28-nm / Majority Logic / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 3, ICD2016-3, pp. 13-16, April 2016.
Paper # ICD2016-3 
Date of Issue 2016-04-07 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2016-04-14 - 2016-04-15 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2016-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor 
Sub Title (in English)  
Keyword(1) Image Memory  
Keyword(2) Multiport SRAM  
Keyword(3) 8T  
Keyword(4) FD-SOI  
Keyword(5) 28-nm  
Keyword(6) Majority Logic  
Keyword(7)  
Keyword(8)  
1st Author's Name Haruki Mori  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Tomoki Nakagawa  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Yuki Kitahara  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Yuta Kawamoto  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Kenta Takagi  
5th Author's Affiliation Kobe University (Kobe Univ.)
6th Author's Name Shusuke Yoshimoto  
6th Author's Affiliation Kobe University (Kobe Univ.)
7th Author's Name Shintaro Izumi  
7th Author's Affiliation Kobe University (Kobe Univ.)
8th Author's Name Koji Nii  
8th Author's Affiliation Renesas Electronics Corporation (Renesas Electronics)
9th Author's Name Hiroshi Kawaguchi  
9th Author's Affiliation Kobe University (Kobe Univ.)
10th Author's Name Masahiko Yoshimoto  
10th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2016-04-14 11:00:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2016-3 
Volume (vol) vol.116 
Number (no) no.3 
Page pp.13-16 
#Pages 4 
Date of Issue 2016-04-07 (ICD) 

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