| 講演抄録/キーワード |
| 講演名 |
2016-04-14 14:15
[依頼講演]ReRAM reliability characterization and improvement by machine learning ○Tomoko Ogura Iwasaki・Sheyang Ning・Hiroki Yamazawa・Chao Sun・Shuhei Tanakamaru・Ken Takeuchi(Chuo Univ.) ICD2016-8 |
| 抄録 |
(和) |
The low voltage and fast program capability of ReRAM is very attractive for next-generation memory applications, but there also exist new reliability issues associated with the resistance switching mechanism. In this work, the variable behavior of ReRAM memory cells is studied using machine learning (ML) techniques. Prediction of two types of cell behavior are also evaluated, (i) how quickly will the cell reset in the next cycle, and (ii) how the cell will fail after endurance cycling. Furthermore, a new scheme, called Proactive Bit Redundancy, is included into the SSD controller. Here, a ML trained model predicts fail cells and replaces them by dynamic redundancy. In order to eliminate the need for extra address tables to store the failed cell locations, an Invalid Masking technique is also proposed. Based on measured results from a 50nm AlxOy ReRAM testchip, a bit error rate (BER) reduction of 2.85?~, also equivalent to an endurance improvement of 13?~, is obtained with little circuitry overhead. |
| (英) |
The low voltage and fast program capability of ReRAM is very attractive for next-generation memory applications, but there also exist new reliability issues associated with the resistance switching mechanism. In this work, the variable behavior of ReRAM memory cells is studied using machine learning (ML) techniques. Prediction of two types of cell behavior are also evaluated, (i) how quickly will the cell reset in the next cycle, and (ii) how the cell will fail after endurance cycling. Furthermore, a new scheme, called Proactive Bit Redundancy, is included into the SSD controller. Here, a ML trained model predicts fail cells and replaces them by dynamic redundancy. In order to eliminate the need for extra address tables to store the failed cell locations, an Invalid Masking technique is also proposed. Based on measured results from a 50nm AlxOy ReRAM testchip, a bit error rate (BER) reduction of 2.85?~, also equivalent to an endurance improvement of 13?~, is obtained with little circuitry overhead. |
| キーワード |
(和) |
ReRAM / reliability / machine learning / proactive redundancy / / / / |
| (英) |
ReRAM / reliability / machine learning / proactive redundancy / / / / |
| 文献情報 |
信学技報, vol. 116, no. 3, ICD2016-8, pp. 39-44, 2016年4月. |
| 資料番号 |
ICD2016-8 |
| 発行日 |
2016-04-07 (ICD) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| PDFダウンロード |
ICD2016-8 |
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