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Paper Abstract and Keywords
Presentation 2016-04-21 10:45
Parallel Implementation of Cipher on CPU/GPU for Programmable Optical Access Equipment
Takahiro Suzuki, Sang-Yuep Kim, Jun-ichi Kani, Ken-Ichi Suzuki, Akihiro Otaka (NTT) CS2016-1
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, NFV and SDN are attracting attention with the goal being enhanced networks efficiency. In access network, software implementation of functions of communications equipment is pursued for speeding service provision and CAPEX/OPEX reduction by commonalizing and integrated equipment of plural services. This paper proposes the programmable OLT; it performs OLT functions by software processing on general-purpose hardware. To accomplish the programmable OLT, the problem is to achieve requested throughput of access equipment on general-purpose hardware. We evaluated throughput of functions of PON system, modulation/demodulation signal processing, error correction and cipher, on simulator of many-core CPU and show a consider policy. In addition, cipher algorithm is implemented on CPU/GPU. The results show throughput of 1.12 Gbps with CTR-AES-128 and 1.13 Gbps with GCM-AES-128 on CPU. In addition, they show throughput of 5.37 Gbps with CTR-AES-128 and 914 Mbps with GCM-AES-128 on GPU. They show the feasibility of software implementation of 1-Gbps-class cipher processing.
Keyword (in Japanese) (See Japanese page) 
(in English) Access network / NFV / Cipher / Parallelization / GPU / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 9, CS2016-1, pp. 1-6, April 2016.
Paper # CS2016-1 
Date of Issue 2016-04-14 (CS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CS CQ NV  
Conference Date 2016-04-21 - 2016-04-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) SDN (Software-Defined Networking), NFV(Network Functions. Virtualization), Network Virtualization, Cloud, Service Quality, Contents Delivery, etc 
Paper Information
Registration To CS 
Conference Code 2016-04-CS-CQ-NV 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Parallel Implementation of Cipher on CPU/GPU for Programmable Optical Access Equipment 
Sub Title (in English)  
Keyword(1) Access network  
Keyword(2) NFV  
Keyword(3) Cipher  
Keyword(4) Parallelization  
Keyword(5) GPU  
1st Author's Name Takahiro Suzuki  
1st Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
2nd Author's Name Sang-Yuep Kim  
2nd Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
3rd Author's Name Jun-ichi Kani  
3rd Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
4th Author's Name Ken-Ichi Suzuki  
4th Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
5th Author's Name Akihiro Otaka  
5th Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
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Speaker Author-1 
Date Time 2016-04-21 10:45:00 
Presentation Time 25 minutes 
Registration for CS 
Paper # CS2016-1 
Volume (vol) vol.116 
Number (no) no.9 
Page pp.1-6 
Date of Issue 2016-04-14 (CS) 

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