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Paper Abstract and Keywords
Presentation 2016-05-11 13:50
Multi bit soft error tolerant FPGA architecture
Yuji Nakamura, Takuya Teraoka, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) VLD2016-3
Abstract (in Japanese) (See Japanese page) 
(in English) Due to reaching the nanoscale transistor size, effect of soft error to the memory has become conspicuous. In small device geometries, a single particle strike might affect multiple adjacent cells in a memory array resulting in a MBU (Multiple Bit Upset). Traditional fault tolerance technologies such as TMR (Triple Modular Redundancy) and ECC (Error Correcting Code) occupy the large area and have vulnerability to MBU. In this research, we propose DMR (Double Modular Redundancy) based error correct circuit and employ a combination of proposed circuit and the interleaving technique to mitigate MBU. In addition, we explain soft error simulator developed to calculate bit interleaving distance. The results show that the area of proposed circuit is the smallest when we compare the proposed circuit, ECC based error correct circuit and TMR. Simulation results show that the interleaving distance which can conceal all MBU patterns is 4.
Keyword (in Japanese) (See Japanese page) 
(in English) Soft error / MBU / Bit interleaving technique / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 21, VLD2016-3, pp. 35-40, May 2016.
Paper # VLD2016-3 
Date of Issue 2016-05-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-3

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2016-05-11 - 2016-05-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2016-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Multi bit soft error tolerant FPGA architecture 
Sub Title (in English)  
Keyword(1) Soft error  
Keyword(2) MBU  
Keyword(3) Bit interleaving technique  
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1st Author's Name Yuji Nakamura  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Takuya Teraoka  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Morihiro Kuga  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
6th Author's Name Toshinori Sueyoshi  
6th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2016-05-11 13:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-3 
Volume (vol) vol.116 
Number (no) no.21 
Page pp.35-40 
#Pages 6 
Date of Issue 2016-05-04 (VLD) 

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