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Paper Abstract and Keywords
Presentation 2016-06-02 16:10
[Invited Talk] Modeling and Measuring Vertical Interconnects with Impedance Control Over a Wide Frequency Range
Kuan-Chung Lu, Tzyy-Sheng Horng (National Sun Yat-sen Univ.) EMCJ2016-35
Abstract (in Japanese) (See Japanese page) 
(in English) The advantages of vertical interconnects include superior electrical transmissions for stacked dies, higher I/O density, and heterogeneous integration. Despite the shorter physical length and superior electrical properties of the vertical interconnects, the arrangement of corresponding grounding pins drastically affects the characteristic impedance, resulting in impedance mismatch during the propagation of signals, which leads to signal reflection. Therefore, to potentially overcome this disadvantage, this work endeavors to establish the analytical model of the vertical interconnects for improving the impedance matching design. The key approach is to use the method of image charges for analyzing the substrate parasitic capacitance between the signal pin and grounding pins of the vertical interconnect. The proposed physical models are capable of predicting accurately the changes in characteristic impedance of various grounding pin arrangements in the vertical interconnect, and based on the prediction results the optimal impedance-matching design can be found. In this work, two types of vertical interconnects, through-silicon via (TSV) and pogo pin, are compared for discussion. Two physical models, one for single-ended signaling and the other for differential signaling, are developed to analyze how changes in TSV pitch-to-diameter ratio affect the characteristic impedance. Moreover, the same physical models are utilized to predict the changes in characteristic impedance caused by the alteration in the substrate parasitic capacitance between signal pin and grounding pins, under the circumstance that the information through the pogo pins is transmitted by single-ended signals with four different types of symmetric grounding architecture.

The experiment in this work aims to improve the traditional coplanar probe stations used for measuring vertical interconnects. Traditionally, to extract the frequency response of the vertical interconnects under test, complex de-embedding techniques are required to calibrate out the parasitic effects of the test vehicle. However, the effective calibration bandwidth is limited. In response to this disadvantage, this work develops a double-sided probe station and calibrates the station with the help of a zero-delay thru. This setup can avoid the complex de-embedding process to measure the high frequency electrical properties of vertical interconnects in a more direct, accurate, and rapid manner. Compared to traditional means, the proposed method significantly enhances the measurement bandwidth. Finally, comparisons of S-parameters among the modeled, EM-simulated and measured results for the TSV and pogo pin structures are obtained. The comparisons demonstrate very good agreement, thereby verifying the proposed physical modeling methods for the vertical interconnects over a wide frequency range.
Keyword (in Japanese) (See Japanese page) 
(in English) Vertical interconnect / through-silicon via / pogo pin / method of image charges / broadband physical model / double-sided probing system / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 72, EMCJ2016-35, pp. 57-62, June 2016.
Paper # EMCJ2016-35 
Date of Issue 2016-05-26 (EMCJ) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF EMCJ2016-35

Conference Information
Committee EMCJ IEE-EMC IEE-MAG  
Conference Date 2016-06-02 - 2016-06-03 
Place (in Japanese) (See Japanese page) 
Place (in English) NTU, Taiwan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) EMC Joint Workshop, 2016, Taipei 
Paper Information
Registration To EMCJ 
Conference Code 2016-06-EMCJ-EMC-MAG 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Modeling and Measuring Vertical Interconnects with Impedance Control Over a Wide Frequency Range 
Sub Title (in English)  
Keyword(1) Vertical interconnect  
Keyword(2) through-silicon via  
Keyword(3) pogo pin  
Keyword(4) method of image charges  
Keyword(5) broadband physical model  
Keyword(6) double-sided probing system  
Keyword(7)  
Keyword(8)  
1st Author's Name Kuan-Chung Lu  
1st Author's Affiliation National Sun Yat-sen University (National Sun Yat-sen Univ.)
2nd Author's Name Tzyy-Sheng Horng  
2nd Author's Affiliation National Sun Yat-sen University (National Sun Yat-sen Univ.)
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Speaker Author-1 
Date Time 2016-06-02 16:10:00 
Presentation Time 50 minutes 
Registration for EMCJ 
Paper # EMCJ2016-35 
Volume (vol) vol.116 
Number (no) no.72 
Page pp.57-62 
#Pages 6 
Date of Issue 2016-05-26 (EMCJ) 

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