Paper Abstract and Keywords |
Presentation |
2016-06-16 10:10
Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient Conrad JinYong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. of Tokyo) CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
As fabricated circuitry gets larger and denser, modern industrial ATPG techniques which focus on the detection of single faults become more likely to overlook multiple (simultaneous) faults. Although there are exponentially more multiple faults than single faults, previous works have shown that given an initial set of test patterns for single faults, relatively few additional tests are required in order to cover all multiple faults. The exact situations in which test patterns generated by ATPG for single stuck-at (SSA) faults do not detect multiple stuck-at (MSA) faults will be examined. This will be done by presenting proofs which show the conditions that need to be met such that ATPG for single faults can cover all multiple faults. An analysis is then performed to determine the exact conditions that, when removed from the circuit, violate the assumption that ATPG for single faults will detect all multiple faults. Finally, our proposed ATPG algorithm will be explained. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Automatic Test Pattern Generation / Double Fault / Single Fault / Combinational Logic / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 94, VLD2016-9, pp. 13-18, June 2016. |
Paper # |
VLD2016-9 |
Date of Issue |
2016-06-09 (CAS, VLD, SIP, MSS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3 |
Conference Information |
Committee |
VLD CAS MSS SIP |
Conference Date |
2016-06-16 - 2016-06-17 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hirosaki Shiritsu Kanko-kan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System, signal processing and related topics |
Paper Information |
Registration To |
VLD |
Conference Code |
2016-06-VLD-CAS-MSS-SIP |
Language |
English (Japanese title is available) |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient |
Sub Title (in English) |
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Keyword(1) |
Automatic Test Pattern Generation |
Keyword(2) |
Double Fault |
Keyword(3) |
Single Fault |
Keyword(4) |
Combinational Logic |
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1st Author's Name |
Conrad JinYong Moore |
1st Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Amir Masoud Gharehbaghi |
2nd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Masahiro Fujita |
3rd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2016-06-16 10:10:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
CAS2016-3, VLD2016-9, SIP2016-37, MSS2016-3 |
Volume (vol) |
vol.116 |
Number (no) |
no.93(CAS), no.94(VLD), no.95(SIP), no.96(MSS) |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2016-06-09 (CAS, VLD, SIP, MSS) |
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