IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2016-06-16 10:10
Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient
Conrad JinYong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita (Univ. of Tokyo) CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3
Abstract (in Japanese) (See Japanese page) 
(in English) As fabricated circuitry gets larger and denser, modern industrial ATPG techniques which focus on the detection of single faults become more likely to overlook multiple (simultaneous) faults. Although there are exponentially more multiple faults than single faults, previous works have shown that given an initial set of test patterns for single faults, relatively few additional tests are required in order to cover all multiple faults. The exact situations in which test patterns generated by ATPG for single stuck-at (SSA) faults do not detect multiple stuck-at (MSA) faults will be examined. This will be done by presenting proofs which show the conditions that need to be met such that ATPG for single faults can cover all multiple faults. An analysis is then performed to determine the exact conditions that, when removed from the circuit, violate the assumption that ATPG for single faults will detect all multiple faults. Finally, our proposed ATPG algorithm will be explained.
Keyword (in Japanese) (See Japanese page) 
(in English) Automatic Test Pattern Generation / Double Fault / Single Fault / Combinational Logic / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 94, VLD2016-9, pp. 13-18, June 2016.
Paper # VLD2016-9 
Date of Issue 2016-06-09 (CAS, VLD, SIP, MSS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CAS2016-3 VLD2016-9 SIP2016-37 MSS2016-3

Conference Information
Committee VLD CAS MSS SIP  
Conference Date 2016-06-16 - 2016-06-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Hirosaki Shiritsu Kanko-kan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System, signal processing and related topics 
Paper Information
Registration To VLD 
Conference Code 2016-06-VLD-CAS-MSS-SIP 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient 
Sub Title (in English)  
Keyword(1) Automatic Test Pattern Generation  
Keyword(2) Double Fault  
Keyword(3) Single Fault  
Keyword(4) Combinational Logic  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Conrad JinYong Moore  
1st Author's Affiliation The University of Tokyo (Univ. of Tokyo)
2nd Author's Name Amir Masoud Gharehbaghi  
2nd Author's Affiliation The University of Tokyo (Univ. of Tokyo)
3rd Author's Name Masahiro Fujita  
3rd Author's Affiliation The University of Tokyo (Univ. of Tokyo)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2016-06-16 10:10:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # CAS2016-3, VLD2016-9, SIP2016-37, MSS2016-3 
Volume (vol) vol.116 
Number (no) no.93(CAS), no.94(VLD), no.95(SIP), no.96(MSS) 
Page pp.13-18 
#Pages
Date of Issue 2016-06-09 (CAS, VLD, SIP, MSS) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan