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Paper Abstract and Keywords
Presentation 2016-06-20 15:40
Partially Parallel Time Domain Reed Solomon Decoder
Kentaro Kato (NIT, Tsuruoka College), Somsak Choomchuay (KMITL) DC2016-15
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a partially parallel time domain reed solomon decoder to reduce the decoding
time. The proposed decoder decodes the encoded data with both parallel data processing and time multiplexed
data processing. The multiple data paths are constructed in the decoder for multiple data processing. The
decoding time, area, and power of the proposed decoder can be optimized with adjusting the parallelism. The
partially parallel time domain RS(15, 11) decoder is implemented with Cycline III FPGA with cylone III Starter
Kit. The evaluation results show that the data throughput of the proposed partial parallel decoding approach
exceeds maximum data throughput of the serial decoding approach when the parallelism is larger than 4. The
maximum increase ratio of the data throughput, area overhead, and power overhead are 287.0 %, 192.8 %, and 21.7
%, respectively when the prallelism is 8.
Keyword (in Japanese) (See Japanese page) 
(in English) time domain reed solomon decoding / FPGA-based decoder / partially parallel architecture / parallel decoding / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 108, DC2016-15, pp. 31-36, June 2016.
Paper # DC2016-15 
Date of Issue 2016-06-13 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2016-15

Conference Information
Committee DC  
Conference Date 2016-06-20 - 2016-06-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design, Test, Verification, etc. 
Paper Information
Registration To DC 
Conference Code 2016-06-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Partially Parallel Time Domain Reed Solomon Decoder 
Sub Title (in English)  
Keyword(1) time domain reed solomon decoding  
Keyword(2) FPGA-based decoder  
Keyword(3) partially parallel architecture  
Keyword(4) parallel decoding  
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1st Author's Name Kentaro Kato  
1st Author's Affiliation National Institute of Technology, Tsuruoka College (NIT, Tsuruoka College)
2nd Author's Name Somsak Choomchuay  
2nd Author's Affiliation King Monkut's Institute of Technology, Ladkrabang (KMITL)
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Speaker Author-1 
Date Time 2016-06-20 15:40:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2016-15 
Volume (vol) vol.116 
Number (no) no.108 
Page pp.31-36 
#Pages
Date of Issue 2016-06-13 (DC) 


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