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Paper Abstract and Keywords
Presentation 2016-09-06 13:50
An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation
Daichi Murata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) RECONF2016-38
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents an efficient and small-scaled RNN (Recurrent Neural Network) hardware architecture based on approximation of RNN algorithm for hardware implementation.
In an LSTM (Long Short-Term Memory) layer, using an approximate function instead of sigmoid function and hyperbolic function is the key to save hardware resources while keeping the accuracy of RNN results. Moreover, we propose a technique to reduce latency by simplifying pooling layer.
Experimental results have shown that our LSTM architecture using the approximate function reduces computing element area by 88.6%, and memory element area by 79.1% while keeping the accuracy of RNN results. Moreover, the proposed pooling hardware architecture reduces latency by 84.3%.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / RNN / LSTM / Function Approximation / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 210, RECONF2016-38, pp. 69-74, Sept. 2016.
Paper # RECONF2016-38 
Date of Issue 2016-08-29 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2016-38

Conference Information
Committee RECONF  
Conference Date 2016-09-05 - 2016-09-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Univ. of Toyama 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2016-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) RNN  
Keyword(3) LSTM  
Keyword(4) Function Approximation  
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1st Author's Name Daichi Murata  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Tetsuya Hirose  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Nobutaka Kuroki  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Masahiro Numa  
4th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2016-09-06 13:50:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2016-38 
Volume (vol) vol.116 
Number (no) no.210 
Page pp.69-74 
#Pages 6 
Date of Issue 2016-08-29 (RECONF) 

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