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| Paper Abstract and Keywords | ||
| Presentation | 2016-11-29 10:30 Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.)  RECONF2016-45 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$overline{A}$ LUT is a new programmable logic using atom switches. A unique feature of 0-1-$A$-$overline{A}$ LUT is that the fanout of the input buffers that is connected to the switch matrix for driving MUX's inputs depends on the mapped logic function. This paper proposes a delay model that reflects this feature and a delay optimal technology mapping algorithms using it. During $k$-feasible cut selection, our algorithms use delay information of our LUT that is classified by the number of MUX's inputs its drives. From our experiments, the circuit delay using our $k$-LUT is 46% smaller in the best case compared with using the conventional atom-switch-based $k$-LUT. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | atom switch / technology mapping / K-feasible cut / reconfigurable device architecture / nano-scale device / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 332, RECONF2016-45, pp. 29-34, Nov. 2016. | |
| Paper # | RECONF2016-45 | |
| Date of Issue | 2016-11-21 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2016-45 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE |
| Conference Date | 2016-11-28 - 2016-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm |
| Sub Title (in English) | |
| Keyword(1) | atom switch |
| Keyword(2) | technology mapping |
| Keyword(3) | K-feasible cut |
| Keyword(4) | reconfigurable device architecture |
| Keyword(5) | nano-scale device |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Toshiki Higashi |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Hiroyuki Ochi |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2016-11-29 10:30:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2016-45 |
| Volume (vol) | vol.116 |
| Number (no) | no.332 |
| Page | pp.29-34 |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (RECONF) |
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