Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2016-11-30 09:00
Fast Test Pattern Reordering Based on Weighted Fault Coverage
Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.) VLD2016-61 DC2016-55
Abstract (in Japanese) (See Japanese page) 
(in English) Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap between the defect level estimation at the design stage and the reported one for fabricated devices. Authors have proposed a technique that can lower the defect level for shipped VLSI chips. In this study, considering bridge and open faults, we propose fast test pattern reordering techniques. Based on distribution of critical area, we make two fault groups. Test generation is performed targeting each fault group, then the reordering is only applied to the second test pattern set. We also show the window-based reordering. Compared to the previous reordering, the proposed scheme significantly reduce processing time while test pattern count slightly increases.
Keyword (in Japanese) (See Japanese page) 
(in English) critical area / weighted fault coverage / bridge fault / open fault / test generation / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 331, DC2016-55, pp. 99-104, Nov. 2016.
Paper # DC2016-55 
Date of Issue 2016-11-21 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-61 DC2016-55

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE  
Conference Date 2016-11-28 - 2016-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2016 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Fast Test Pattern Reordering Based on Weighted Fault Coverage 
Sub Title (in English)  
Keyword(1) critical area  
Keyword(2) weighted fault coverage  
Keyword(3) bridge fault  
Keyword(4) open fault  
Keyword(5) test generation  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shingo Inuyama  
1st Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
2nd Author's Name Kazuhiko Iwasaki  
2nd Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
3rd Author's Name Masayuki Arai  
3rd Author's Affiliation Nihon University (Nihon Univ.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2016-11-30 09:00:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2016-61, DC2016-55 
Volume (vol) vol.116 
Number (no) no.330(VLD), no.331(DC) 
Page pp.99-104 
#Pages 6 
Date of Issue 2016-11-21 (VLD, DC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan