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Paper Abstract and Keywords
Presentation 2016-11-30 13:45
Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis
Daisuke Ishikawa, Kenshu Seto (TCU) VLD2016-69 DC2016-63
Abstract (in Japanese) (See Japanese page) 
(in English) We propose data transfer optimization in accelerator design with high-level synthesis. Typical accelerator designs perform data transfer and computation separately. So that, all required data are stored in internal memory before computation. Such previous accelerator design techniques have two problems, namely, more clock cycles and increased area. This is because the previous techniques require extra cycles for data transfer and a large size of data reuse buffers. Accelerator designed by our technique perform computation and data transfer at the same time. Therefore, our technique can reduce the number of clock cycles for accelerators. Moreover, our technique can reduce hardware area by reducing the size of buffer memories.
Keyword (in Japanese) (See Japanese page) 
(in English) High-Level Synthesis / Data Transfer Optimization / Hardware accelerator / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 330, VLD2016-69, pp. 147-152, Nov. 2016.
Paper # VLD2016-69 
Date of Issue 2016-11-21 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-69 DC2016-63

Conference Information
Committee VLD DC CPSY RECONF CPM ICD IE  
Conference Date 2016-11-28 - 2016-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Ritsumeikan University, Osaka Ibaraki Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2016 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2016-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis 
Sub Title (in English)  
Keyword(1) High-Level Synthesis  
Keyword(2) Data Transfer Optimization  
Keyword(3) Hardware accelerator  
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1st Author's Name Daisuke Ishikawa  
1st Author's Affiliation Tokyo City University (TCU)
2nd Author's Name Kenshu Seto  
2nd Author's Affiliation Tokyo City University (TCU)
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Speaker Author-1 
Date Time 2016-11-30 13:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-69, DC2016-63 
Volume (vol) vol.116 
Number (no) no.330(VLD), no.331(DC) 
Page pp.147-152 
#Pages 6 
Date of Issue 2016-11-21 (VLD, DC) 

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