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Paper Abstract and Keywords
Presentation 2016-12-21 15:30
Theoretical Model of Interconnection Networks Consisting of Hosts and Switches
Ryota Yasudo (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.), Koji Nakano (Hiroshima Univ.) ISEC2016-79 COMP2016-40
Abstract (in Japanese) (See Japanese page) 
(in English) Designing interconnection networks with low average shortest path length (ASPL) is an important object for researchers on computer systems. To this end, theoretical study is becoming essential. This work thus presents a host-switch graph, a theoretical model of interconnection networks. Interconnection networks consist of hosts and switches, and hence this model distinguishes between them. Designers’ goal is to construct a host-switch graph with the lowest ASPL between hosts for a given number of hosts and ports per switch. We provide the lower bound of the ASPL and study both deterministic and heuristic approaches. As a deterministic approach, we introduce typical host-switch graphs and discuss their ASPLs. We show a host-switch graph based on a clique provides the lowest ASPL, if it is constructable. As a heuristic approach, we study a randomized algorithm for host-switch graph. This approach must fix the number of switches. Hence, we carry out numerical simulations for various numbers of switches. Our results indicate the optimal number of switches can be predicted by the Moore bound, the known lower bound of the ASPL of regular undirected graphs.
Keyword (in Japanese) (See Japanese page) 
(in English) interconnection networks / graph theory / average shortest path length / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 381, COMP2016-40, pp. 51-58, Dec. 2016.
Paper # COMP2016-40 
Date of Issue 2016-12-14 (ISEC, COMP) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee COMP ISEC  
Conference Date 2016-12-21 - 2016-12-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiroshima University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To COMP 
Conference Code 2016-12-COMP-ISEC 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Theoretical Model of Interconnection Networks Consisting of Hosts and Switches 
Sub Title (in English)  
Keyword(1) interconnection networks  
Keyword(2) graph theory  
Keyword(3) average shortest path length  
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1st Author's Name Ryota Yasudo  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Michihiro Koibuchi  
2nd Author's Affiliation National Institute of Informatics (NII)
3rd Author's Name Hideharu Amano  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Koji Nakano  
4th Author's Affiliation Hiroshima University (Hiroshima Univ.)
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Speaker Author-1 
Date Time 2016-12-21 15:30:00 
Presentation Time 20 minutes 
Registration for COMP 
Paper # ISEC2016-79, COMP2016-40 
Volume (vol) vol.116 
Number (no) no.380(ISEC), no.381(COMP) 
Page pp.51-58 
#Pages 8 
Date of Issue 2016-12-14 (ISEC, COMP) 

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