Paper Abstract and Keywords |
Presentation |
2017-01-23 13:50
GRAPE9-MPX: development of an accelerator system dedicated for multi-precision arithmetic operations and its application Hiroshi Daisaka (Hitotsubashi Univ.), Naohito Nakasato (Univ. of Aizu), Tadashi Ishikawa, Fukuko Yuasa (KEK), Keigo Nitadori (RIKEN/AICS) VLD2016-72 CPSY2016-108 RECONF2016-53 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have been developing GRAPE9-MPX which is a dedicated system to accelerate the computation with multi precision arithmetic operations.
In this system, we implemented Processor Elements (PE)
to realize the quadruple/hexuple/octuple-precision arithmetics in FPGA.
We have constructed a system that consists of up to 16 FPGA board on a host computer, and have shown its validation by performing numerical integration of Feynman loop diagram.
Here we report the construction of our new system which consists of 48 FPGA boards with improved processor, our development environment, and its performance results by performing numerical integration of Feynman loop diagram. We also report the implementation results of our processor
on new FPGA devices. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
multiple-precision arithmetic / quadruple/hexuple/octuple precision / FPGA / Feynman amplitude / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 417, RECONF2016-53, pp. 13-18, Jan. 2017. |
Paper # |
RECONF2016-53 |
Date of Issue |
2017-01-16 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-72 CPSY2016-108 RECONF2016-53 |
Conference Information |
Committee |
CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC |
Conference Date |
2017-01-23 - 2017-01-25 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hiyoshi Campus, Keio Univ. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA Applications, etc |
Paper Information |
Registration To |
RECONF |
Conference Code |
2017-01-CPSY-RECONF-VLD-SLDM-ARC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
GRAPE9-MPX: development of an accelerator system dedicated for multi-precision arithmetic operations and its application |
Sub Title (in English) |
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Keyword(1) |
multiple-precision arithmetic |
Keyword(2) |
quadruple/hexuple/octuple precision |
Keyword(3) |
FPGA |
Keyword(4) |
Feynman amplitude |
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1st Author's Name |
Hiroshi Daisaka |
1st Author's Affiliation |
Hitotsubashi University (Hitotsubashi Univ.) |
2nd Author's Name |
Naohito Nakasato |
2nd Author's Affiliation |
University of Aizu (Univ. of Aizu) |
3rd Author's Name |
Tadashi Ishikawa |
3rd Author's Affiliation |
High Energy Accelerator Research Organization (KEK) |
4th Author's Name |
Fukuko Yuasa |
4th Author's Affiliation |
High Energy Accelerator Research Organization (KEK) |
5th Author's Name |
Keigo Nitadori |
5th Author's Affiliation |
RIKEN Advanced Institute for Computational Science (RIKEN/AICS) |
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Speaker |
Author-1 |
Date Time |
2017-01-23 13:50:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
VLD2016-72, CPSY2016-108, RECONF2016-53 |
Volume (vol) |
vol.116 |
Number (no) |
no.415(VLD), no.416(CPSY), no.417(RECONF) |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2017-01-16 (VLD, CPSY, RECONF) |
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