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Paper Abstract and Keywords
Presentation 2017-01-23 15:45
Distributed Handshake-Join Processing for Stream Data on Multiple FPGA Nodes
Kousuke Tada, Naoto Kawahara, Masato Yoshimi, Celimuge, Wu., Tsutomu Yoshinaga (UEC) VLD2016-76 CPSY2016-112 RECONF2016-57
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes an FPGA-based Handshake join acceleration using multiple-FPGA boards.
The proposed multi-node extension devises two ideas.
Firstly, join cores implemented on each FPGA are interconnected via DRAM on the FPGA boards.
Secondly, join operation is overlapped with data transmission between FPGAs in order to hide communication latency.
The proposed architecture performs Handshake join algorithm well on mul-tiple FPGA boards,
and a window size can be expanded linearly as the number of FPGAs.
Our experiments up to 16 FPGA nodes show that the proposed implementation can handle considerably high input tuple rates,
especially at low match rates, without degrading performance even for a large window size.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Stream Data Processing / Window Join Operator / Handshake Join / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 416, CPSY2016-112, pp. 37-42, Jan. 2017.
Paper # CPSY2016-112 
Date of Issue 2017-01-16 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-76 CPSY2016-112 RECONF2016-57

Conference Information
Committee CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC  
Conference Date 2017-01-23 - 2017-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To CPSY 
Conference Code 2017-01-CPSY-RECONF-VLD-SLDM-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Distributed Handshake-Join Processing for Stream Data on Multiple FPGA Nodes 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Stream Data Processing  
Keyword(3) Window Join Operator  
Keyword(4) Handshake Join  
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1st Author's Name Kousuke Tada  
1st Author's Affiliation University of Electro-Communications (UEC)
2nd Author's Name Naoto Kawahara  
2nd Author's Affiliation University of Electro-Communications (UEC)
3rd Author's Name Masato Yoshimi  
3rd Author's Affiliation University of Electro-Communications (UEC)
4th Author's Name Celimuge, Wu.  
4th Author's Affiliation University of Electro-Communications (UEC)
5th Author's Name Tsutomu Yoshinaga  
5th Author's Affiliation University of Electro-Communications (UEC)
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Speaker Author-1 
Date Time 2017-01-23 15:45:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # VLD2016-76, CPSY2016-112, RECONF2016-57 
Volume (vol) vol.116 
Number (no) no.415(VLD), no.416(CPSY), no.417(RECONF) 
Page pp.37-42 
#Pages
Date of Issue 2017-01-16 (VLD, CPSY, RECONF) 


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