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Paper Abstract and Keywords
Presentation 2017-01-24 17:20
A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption
Kazumasa Ishikawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2016-92 CPSY2016-128 RECONF2016-73
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we presented a new residue addition algorithm using Signed-Digit (SD) numbers for the applications such as RSA encryption with very long word-length. In the proposed algorithm, for the high-speed residue SD addition with $n$ digits, a residue parameter: $\mu (=m-2^n)$ is used for the residue operation instead of using $m$($2^{n-1}<m<2^n$), which is the modulus in the residue arithmetic system. We apply the residue SD addition circuits to implement a RSA encryption processor by using a library with $0.18{\rm \mu m}$ CMOS VLSI technology. The design results show that high speed encryption can be achieved by using the proposed SD arithmetic architecture.
Keyword (in Japanese) (See Japanese page) 
(in English) Signed-Digit(SD) number / residue SD addition / residue SD multiplication / RSA encryption processor / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 415, VLD2016-92, pp. 147-152, Jan. 2017.
Paper # VLD2016-92 
Date of Issue 2017-01-16 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-92 CPSY2016-128 RECONF2016-73

Conference Information
Committee CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC  
Conference Date 2017-01-23 - 2017-01-25 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2017-01-CPSY-RECONF-VLD-SLDM-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption 
Sub Title (in English)  
Keyword(1) Signed-Digit(SD) number  
Keyword(2) residue SD addition  
Keyword(3) residue SD multiplication  
Keyword(4) RSA encryption processor  
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1st Author's Name Kazumasa Ishikawa  
1st Author's Affiliation Gunma University (Gunma Univ.)
2nd Author's Name Yuuki Tanaka  
2nd Author's Affiliation Gunma University (Gunma Univ.)
3rd Author's Name Shugang Wei  
3rd Author's Affiliation Gunma University (Gunma Univ.)
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Speaker Author-1 
Date Time 2017-01-24 17:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-92, CPSY2016-128, RECONF2016-73 
Volume (vol) vol.116 
Number (no) no.415(VLD), no.416(CPSY), no.417(RECONF) 
Page pp.147-152 
#Pages 6 
Date of Issue 2017-01-16 (VLD, CPSY, RECONF) 

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