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| Presentation | 2017-01-25 10:15 MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami (SIT)  VLD2016-97 CPSY2016-133 RECONF2016-78 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With the spread of portable devices in recent year, products with high performance and low power consumption are required. Therefore, as a method of reducing the power consumption of the flip-flop circuit, a nonvolatile flip-flop that enables power gating by using magnetic tunnel junction (MTJ) has been proposed. However, MTJ has a large energy for writing data. Also, if voltage or time is changed in order to reduce energy, write error occurs. Therefore, in this paper, we propose MTJ-based nonvolatile flip-flop circuit enabling to verify stored data and rewrite correct data. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Power-Gating / MTJ / Flip-Flop / Verify / Low Energy Consumption / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 415, VLD2016-97, pp. 175-180, Jan. 2017. | |
| Paper # | VLD2016-97 | |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-97 CPSY2016-133 RECONF2016-78 |
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| Conference Information | |
| Committee | CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2017-01-23 - 2017-01-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2017-01-CPSY-RECONF-VLD-SLDM-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data |
| Sub Title (in English) | |
| Keyword(1) | Power-Gating |
| Keyword(2) | MTJ |
| Keyword(3) | Flip-Flop |
| Keyword(4) | Verify |
| Keyword(5) | Low Energy Consumption |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Junya Akaike |
| 1st Author's Affiliation | Shibaura Institute of Technology (SIT) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology (SIT) |
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| Speaker | Author-1 |
| Date Time | 2017-01-25 10:15:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2016-97, CPSY2016-133, RECONF2016-78 |
| Volume (vol) | vol.116 |
| Number (no) | no.415(VLD), no.416(CPSY), no.417(RECONF) |
| Page | pp.175-180 |
| #Pages | 6 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |
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