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| Presentation | 2017-01-25 09:25 Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH)  VLD2016-95 CPSY2016-131 RECONF2016-76 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | When variable latency for digital circuits are assumed, circuits can work with a small clock period that has the possibility to occur timing errors. If a timing error is detected, a correctness of primitive computation of the circuit is kept by correcting wrong values by a technique such like Razor flip-flop. Approximate computing will realize if we can appropriately control wrong values generated by timing errors. In our research, we aim to realize approximate computing by using general-synchronous circuits which allowed variable latency. In such approach, it is considered that the clock period and input sequences affect the accuracy of outputs of combinational circuits. In this paper, we investigate the influences of input sequences and clock period to the outputs of an adder circuit by a gate level simulation. From the experiments, we found that there is a relation between the delay and the difference of inputs and the average difference of outputs against the correct value is almost 0% when the difference of inputs is small. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Approximate computing, / General-synchronous circuit / variable latency / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 116, no. 415, VLD2016-95, pp. 165-170, Jan. 2017. | |
| Paper # | VLD2016-95 | |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2016-95 CPSY2016-131 RECONF2016-76 |
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| Conference Information | |
| Committee | CPSY RECONF VLD IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2017-01-23 - 2017-01-25 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2017-01-CPSY-RECONF-VLD-SLDM-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit |
| Sub Title (in English) | |
| Keyword(1) | Approximate computing, |
| Keyword(2) | General-synchronous circuit |
| Keyword(3) | variable latency |
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| 1st Author's Name | Shimpei Sato |
| 1st Author's Affiliation | Tokyo Institute of Technology (Tokyo TECH) |
| 2nd Author's Name | Yuta Ukon |
| 2nd Author's Affiliation | Tokyo Institute of Technology (Tokyo TECH) |
| 3rd Author's Name | Atsushi Takahashi |
| 3rd Author's Affiliation | Tokyo Institute of Technology (Tokyo TECH) |
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| Speaker | Author-1 |
| Date Time | 2017-01-25 09:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2016-95, CPSY2016-131, RECONF2016-76 |
| Volume (vol) | vol.116 |
| Number (no) | no.415(VLD), no.416(CPSY), no.417(RECONF) |
| Page | pp.165-170 |
| #Pages | 6 |
| Date of Issue | 2017-01-16 (VLD, CPSY, RECONF) |
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