Paper Abstract and Keywords |
Presentation |
2017-03-01 14:00
Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT) VLD2016-102 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the stored data. To realize this, a non-volatile element such as MTJ is incorporated into a SRAM memory cell and the data in SRAM is written to MTJ before the power off. When applying NVPG to cache in CPU, it is effective to apply it partially by selecting cache lines because energy overhead of writing to MTJ is very large. However, cache lines whose data are not stored into MTJ cause cache miss if they are accessed after PG. This incurs energy consumption by accessing the main memory. In this research, we propose a method to PG of Non-volatile cache and dynamic selection control for storing cache lines. As a result of design and implementation of control circuit for 32 bit CPU based on the MIPS architecture, the proposed method reduces leakage energy by 43% at maximum, compared to the normal circuit operation of the CPU. In addition, it reduces the energy consumption increase by PG by 84% at maximum, compared to the static control method proposed in previous research. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Cache / MTJ / Power-Gating / Low-power / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 478, VLD2016-102, pp. 1-6, March 2017. |
Paper # |
VLD2016-102 |
Date of Issue |
2017-02-22 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2016-102 |
Conference Information |
Committee |
VLD |
Conference Date |
2017-03-01 - 2017-03-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
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(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2017-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines |
Sub Title (in English) |
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Cache |
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MTJ |
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Power-Gating |
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Low-power |
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1st Author's Name |
Shota Enokido |
1st Author's Affiliation |
Shibaura Institute of Technology (SIT) |
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Kimiyoshi Usami |
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Shibaura Institute of Technology (SIT) |
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Speaker |
Author-1 |
Date Time |
2017-03-01 14:00:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2016-102 |
Volume (vol) |
vol.116 |
Number (no) |
no.478 |
Page |
pp.1-6 |
#Pages |
6 |
Date of Issue |
2017-02-22 (VLD) |
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