Paper Abstract and Keywords |
Presentation |
2017-03-01 14:50
Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-104 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Due to the progress of the process technology in LSI, the yield of chips is reduced by the timing violation because of the timing violation after fabrication. Recently, post-silicon delay tuning, which inserts programmable delay elements (PDEs) into the clock tree before fabrication and sets the delays of PDEs to recover timing violation after fabrication, is promising to improve the yield. In an existing method, a PDE is constructed by buffers and a multiplexer and a delay of each PDE is determined by a delay tuning algorithm that finds an optimum solution in polynomial time. However, the power becomes high in the existing PDE structure since all buffers in PDEs are switched when the clock signal is switched. In this paper, a PDE structure and a delay tuning algorithm to reduce the power are proposed. The experimental result shows that the proposed method keeps the high yield and reduces the power compared to the existing method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Post-silicon delay tuning / Programmable delay element (PDE) / Yield improvement / Power reduction / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 116, no. 478, VLD2016-104, pp. 13-18, March 2017. |
Paper # |
VLD2016-104 |
Date of Issue |
2017-02-22 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2016-104 |
Conference Information |
Committee |
VLD |
Conference Date |
2017-03-01 - 2017-03-03 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
|
Paper Information |
Registration To |
VLD |
Conference Code |
2017-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement |
Sub Title (in English) |
|
Keyword(1) |
Post-silicon delay tuning |
Keyword(2) |
Programmable delay element (PDE) |
Keyword(3) |
Yield improvement |
Keyword(4) |
Power reduction |
Keyword(5) |
|
Keyword(6) |
|
Keyword(7) |
|
Keyword(8) |
|
1st Author's Name |
Hayato Mashiko |
1st Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
2nd Author's Name |
Yukihide Kohira |
2nd Author's Affiliation |
The University of Aizu (Univ. of Aizu) |
3rd Author's Name |
|
3rd Author's Affiliation |
() |
4th Author's Name |
|
4th Author's Affiliation |
() |
5th Author's Name |
|
5th Author's Affiliation |
() |
6th Author's Name |
|
6th Author's Affiliation |
() |
7th Author's Name |
|
7th Author's Affiliation |
() |
8th Author's Name |
|
8th Author's Affiliation |
() |
9th Author's Name |
|
9th Author's Affiliation |
() |
10th Author's Name |
|
10th Author's Affiliation |
() |
11th Author's Name |
|
11th Author's Affiliation |
() |
12th Author's Name |
|
12th Author's Affiliation |
() |
13th Author's Name |
|
13th Author's Affiliation |
() |
14th Author's Name |
|
14th Author's Affiliation |
() |
15th Author's Name |
|
15th Author's Affiliation |
() |
16th Author's Name |
|
16th Author's Affiliation |
() |
17th Author's Name |
|
17th Author's Affiliation |
() |
18th Author's Name |
|
18th Author's Affiliation |
() |
19th Author's Name |
|
19th Author's Affiliation |
() |
20th Author's Name |
|
20th Author's Affiliation |
() |
Speaker |
Author-1 |
Date Time |
2017-03-01 14:50:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2016-104 |
Volume (vol) |
vol.116 |
Number (no) |
no.478 |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2017-02-22 (VLD) |
|