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Paper Abstract and Keywords
Presentation 2017-03-02 15:00
Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis
Xiaoguang Li, Mineo Kaneko (JAIST) VLD2016-118
Abstract (in Japanese) (See Japanese page) 
(in English) The performance of data path circuit can be improved by shifting the clock signal arrival time intentionally. In order to reduce the number of skew generation circuits, multi-domain skew scheduling method has been proposed, in which registers are clustered into so-called domains and registers in each domain are driven by a common skew generation circuit, and thus registers in a domain have a common clock skew. In this report, we propose simultaneous domain assignment, register assignment and skew scheduling for multi-domain skew schedule aware high level synthesis. Our approach utilizes feasible skew range of each data for arranging domain assignment, and employs the concept of "Structural Robustness against Delay Variation" for hold-constraint free register assignment.
Keyword (in Japanese) (See Japanese page) 
(in English) multi-domain clock skew scheduling / domain assignment / register binding / high-level synthesis / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 478, VLD2016-118, pp. 85-90, March 2017.
Paper # VLD2016-118 
Date of Issue 2017-02-22 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-118

Conference Information
Committee VLD  
Conference Date 2017-03-01 - 2017-03-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2017-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis 
Sub Title (in English)  
Keyword(1) multi-domain clock skew scheduling  
Keyword(2) domain assignment  
Keyword(3) register binding  
Keyword(4) high-level synthesis  
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1st Author's Name Xiaoguang Li  
1st Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
2nd Author's Name Mineo Kaneko  
2nd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
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Speaker Author-1 
Date Time 2017-03-02 15:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-118 
Volume (vol) vol.116 
Number (no) no.478 
Page pp.85-90 
#Pages 6 
Date of Issue 2017-02-22 (VLD) 

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