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Paper Abstract and Keywords
Presentation 2017-03-02 11:45
Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing
Shun Sugihara, Shimpei Sato, Atsushi Takahashi (Tokyo Tech) VLD2016-114
Abstract (in Japanese) (See Japanese page) 
(in English) In printed circuit board, to meet requirements such as delay and noise,
routing of each net is necessary to achieve its target length.
In recent years, various routing methods have been proposed to achieve the target length of each net, and
good routing results are obtained, but a net with error remains.
In this work, a route modification method to achieve the target length
by correcting the wire length of error net without changing the wire length of the other nets is proposed.
From the experiments, we found that our proposed method corrects
almost all of errors in the case of a pattern which the number of nets
is not so much.
Keyword (in Japanese) (See Japanese page) 
(in English) printed circuit board / single layer / route modification / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 478, VLD2016-114, pp. 73-78, March 2017.
Paper # VLD2016-114 
Date of Issue 2017-02-22 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-114

Conference Information
Committee VLD  
Conference Date 2017-03-01 - 2017-03-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2017-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Partial Route Modification Method to Realize Target Equi-length on Single Layer PCB Routing 
Sub Title (in English)  
Keyword(1) printed circuit board  
Keyword(2) single layer  
Keyword(3) route modification  
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1st Author's Name Shun Sugihara  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Shimpei Sato  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2017-03-02 11:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-114 
Volume (vol) vol.116 
Number (no) no.478 
Page pp.73-78 
#Pages 6 
Date of Issue 2017-02-22 (VLD) 

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