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Paper Abstract and Keywords
Presentation 2017-03-03 09:00
Dynamic Power Optimization for Asynchronous Circuits with Bundled-data Implementation based on the Mobility of Operations
Shunya Hosaka, Hiroshi Saito (Aizu Univ) VLD2016-122
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a dynamic power optimization for asynchronous circuits with bundled-data implementation based on the mobility of operations. The proposed method relaxes the execution time of operations which consume more power while it tightens the execution time of operations which consume less power by applying maximum delay constraints under a given latency constraint. In the experiment, we applied the proposed method to three benchmarks to evaluate area, execution time, dynamic power, and energy. We also compared with synchronous circuits and a method using integer linear programming. As a result, we could reduce dynamic power about 44.8% at the maximum, 12.5% at the average, and we could reduce energy about 41.6% at the maximum, 10.1% at the average.
Keyword (in Japanese) (See Japanese page) 
(in English) VLSI / ASIC / Dynamic Power / Optimization / Mobility / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 478, VLD2016-122, pp. 109-114, March 2017.
Paper # VLD2016-122 
Date of Issue 2017-02-22 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2016-122

Conference Information
Committee VLD  
Conference Date 2017-03-01 - 2017-03-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2017-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Dynamic Power Optimization for Asynchronous Circuits with Bundled-data Implementation based on the Mobility of Operations 
Sub Title (in English)  
Keyword(1) VLSI  
Keyword(2) ASIC  
Keyword(3) Dynamic Power  
Keyword(4) Optimization  
Keyword(5) Mobility  
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1st Author's Name Shunya Hosaka  
1st Author's Affiliation University of Aizu (Aizu Univ)
2nd Author's Name Hiroshi Saito  
2nd Author's Affiliation University of Aizu (Aizu Univ)
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Speaker Author-1 
Date Time 2017-03-03 09:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2016-122 
Volume (vol) vol.116 
Number (no) no.478 
Page pp.109-114 
#Pages 6 
Date of Issue 2017-02-22 (VLD) 

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