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Paper Abstract and Keywords
Presentation 2017-03-03 11:40
Hardware implementation of deep neural networks composed of self-organizing maps
Yuichiro Tanaka, Hakaru Tamukoh (KIT) SIS2016-60
Abstract (in Japanese) (See Japanese page) 
(in English) In this research, we aim to implement deep neural networks (DNNs) composed of self-organizing maps into field programmable gate arrays (FPGAs) to develop a recognition system which is high speed and low power consumption. Reductions of multipliers from DNNs are required since multipliers in FPGA are limited and DNNs includes a lot of multipliers. We propose a hardware oriented algorithm for a DNN composed of self-organizing maps which reduces multipliers from DNNs. In addition, we develop a hardware of the DNN using the proposed hardware oriented algorithm and show simulation results.
Keyword (in Japanese) (See Japanese page) 
(in English) Deep Neural Networks / Deep Learning / Self-Organizing Maps / FPGA / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 482, SIS2016-60, pp. 101-106, March 2017.
Paper # SIS2016-60 
Date of Issue 2017-02-23 (SIS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIS2016-60

Conference Information
Committee SIS  
Conference Date 2017-03-02 - 2017-03-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Kanagawa Inst. Tech. Yokohama Office 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Soft Computing, etc. 
Paper Information
Registration To SIS 
Conference Code 2017-03-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Hardware implementation of deep neural networks composed of self-organizing maps 
Sub Title (in English)  
Keyword(1) Deep Neural Networks  
Keyword(2) Deep Learning  
Keyword(3) Self-Organizing Maps  
Keyword(4) FPGA  
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1st Author's Name Yuichiro Tanaka  
1st Author's Affiliation Kyushu Institute of Technology (KIT)
2nd Author's Name Hakaru Tamukoh  
2nd Author's Affiliation Kyushu Institute of Technology (KIT)
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Speaker Author-1 
Date Time 2017-03-03 11:40:00 
Presentation Time 20 minutes 
Registration for SIS 
Paper # SIS2016-60 
Volume (vol) vol.116 
Number (no) no.482 
Page pp.101-106 
#Pages 6 
Date of Issue 2017-02-23 (SIS) 

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