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Paper Abstract and Keywords
Presentation 2017-03-03 10:50
Speeding up using Parallel-Serial conversion in FPGA implementation of quadrature modulation Envelope Pulse Width Modulation Transmitter
Kouhei Nagasawa, Yohtaro Umeda, Yusuke Kozawa (Tokyo Univ. of Science) MW2016-207 ICD2016-137
Abstract (in Japanese) (See Japanese page) 
(in English) This paper presents a new configuration using a serializer on quadrature-modulation (QM) envelope-pulse-width-modulation (EPWM) transmitter with tri-level delta-sigma modulators to generate a bi-level EPWM signal. In the case of implementing the conventional binary QMEPWM transmitter in the FPGA, the limit of the operating frequency of the universal logic module is a problem, so the transmission signal is limited to a low speed. This problem is considered by using a serializer which is a parallel to serial (P/S) conversion device for converting an input parallel signal into a serial signal. However, it has not been considered bi-level quadrature-modulation QM-EPWM transmitter with tri-level delta-sigma modulators. In this research, we propose a configuration to generate a bi-level QM-EPWM signal using tri-level delta-sigma modulators. Evaluate by experiments and compare power spectral density and coding efficiency (CE) with simulation. Furthermore, we will also compare error vector magnitude (EVM) which has not been considered so far
Keyword (in Japanese) (See Japanese page) 
(in English) transmitter / envelope pulse-width modulation / quadrature modulation / FPGA / parallel-to-serial conversion / error vector magnitude / coding efficiency /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 487, ICD2016-137, pp. 107-112, March 2017.
Paper # ICD2016-137 
Date of Issue 2017-02-23 (MW, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF MW2016-207 ICD2016-137

Conference Information
Committee MW ICD  
Conference Date 2017-03-02 - 2017-03-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Okayama Prefectural Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Microwave Integrated Circuit / Microwave Technologies 
Paper Information
Registration To ICD 
Conference Code 2017-03-MW-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Speeding up using Parallel-Serial conversion in FPGA implementation of quadrature modulation Envelope Pulse Width Modulation Transmitter 
Sub Title (in English)  
Keyword(1) transmitter  
Keyword(2) envelope pulse-width modulation  
Keyword(3) quadrature modulation  
Keyword(4) FPGA  
Keyword(5) parallel-to-serial conversion  
Keyword(6) error vector magnitude  
Keyword(7) coding efficiency  
Keyword(8)  
1st Author's Name Kouhei Nagasawa  
1st Author's Affiliation Tokyo University of Science (Tokyo Univ. of Science)
2nd Author's Name Yohtaro Umeda  
2nd Author's Affiliation Tokyo University of Science (Tokyo Univ. of Science)
3rd Author's Name Yusuke Kozawa  
3rd Author's Affiliation Tokyo University of Science (Tokyo Univ. of Science)
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Speaker Author-1 
Date Time 2017-03-03 10:50:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # MW2016-207, ICD2016-137 
Volume (vol) vol.116 
Number (no) no.486(MW), no.487(ICD) 
Page pp.107-112 
#Pages 6 
Date of Issue 2017-02-23 (MW, ICD) 

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