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Paper Abstract and Keywords
Presentation 2017-03-09 15:30
Approach to Direct Memory Access for Tamper Resistant System using Secure Processor
Rihito Suzuki, Takuya Kajiwara, Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai (UTokyo) CPSY2016-138 DC2016-84
Abstract (in Japanese) (See Japanese page) 
(in English) In an environment using secure processor to support secure program execution, because of its integrity check mechanism, DMA (Direct Memory Access) method can not be directly applied. In this paper, we discuss models and designs to realize DMA executed by trusted external devices, which offload IO operation from the processor and guarantee confidentiality / integrity of data.
Keyword (in Japanese) (See Japanese page) 
(in English) secure processors / encrypted computation / direct memory access / / / / /  
Reference Info. IEICE Tech. Rep., vol. 116, no. 510, CPSY2016-138, pp. 39-44, March 2017.
Paper # CPSY2016-138 
Date of Issue 2017-03-02 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2016-138 DC2016-84

Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB IPSJ-ARC  
Conference Date 2017-03-09 - 2017-03-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumejima Island 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ETNET20167 
Paper Information
Registration To CPSY 
Conference Code 2017-03-CPSY-DC-SLDM-EMB-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Approach to Direct Memory Access for Tamper Resistant System using Secure Processor 
Sub Title (in English)  
Keyword(1) secure processors  
Keyword(2) encrypted computation  
Keyword(3) direct memory access  
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1st Author's Name Rihito Suzuki  
1st Author's Affiliation The University of Tokyo (UTokyo)
2nd Author's Name Takuya Kajiwara  
2nd Author's Affiliation The University of Tokyo (UTokyo)
3rd Author's Name Mizuki Miyanaga  
3rd Author's Affiliation The University of Tokyo (UTokyo)
4th Author's Name Hidetsugu Irie  
4th Author's Affiliation The University of Tokyo (UTokyo)
5th Author's Name Shuichi Sakai  
5th Author's Affiliation The University of Tokyo (UTokyo)
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Speaker Author-1 
Date Time 2017-03-09 15:30:00 
Presentation Time 20 minutes 
Registration for CPSY 
Paper # CPSY2016-138, DC2016-84 
Volume (vol) vol.116 
Number (no) no.510(CPSY), no.511(DC) 
Page pp.39-44 
#Pages 6 
Date of Issue 2017-03-02 (CPSY, DC) 

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