Paper Abstract and Keywords |
Presentation |
2017-04-20 16:10
[Invited Talk]
A 512Gb 3b/Cell Flash Memory on 64-Word-Line-Layer BiCS Technology Ryuji Yamashita, Sagar Magia (WDC), Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura (Toshiba), Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang (WDC) ICD2017-9 Link to ES Tech. Rep. Archives: ICD2017-9 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A 512Gb 3b/cell flash has been developed on a 64-WL-layer BiCS technology. By using a four-block-EOC row decoding approach, row decoder area is reduced by 18%, which translates to a 1.3% die size reduction. With additional layout area reduction techniques, a 132mm2 die size and 3.88Gb/mm2 bit density have been achieved. SBL current sensing achieved a 64μs tR with an 8KB page size, which is 20% less than a conventional 16KB-page ABL. USP operation expanded the Vt window by 15%, which has significantly improved endurance and reliability. This work confirms that it is possible to meet market requirements for bit density, cost, performance, and reliability with this 3D-flash technology. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
3D-flash / BiCS / 64-word-line-layer / NAND flash memory / Non-volatile memory / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 9, ICD2017-9, pp. 45-50, April 2017. |
Paper # |
ICD2017-9 |
Date of Issue |
2017-04-13 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2017-9 Link to ES Tech. Rep. Archives: ICD2017-9 |
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