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Paper Abstract and Keywords
Presentation 2017-06-19 11:00
Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation
Ryosuke Koike, Takashi Imagawa (Ritsumeikan Univ.), Roberto Yusi Omaki (Synthesis), Hiroyuki Ochi (Ritsumeikan Univ.) CAS2017-5 VLD2017-8 SIP2017-29 MSS2017-5
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Block can be configured to operate in either fine-grained or coarse-grained mode. Compared with the Mixed Grained Reconfigurable Architecture (MGRA), which has a fixed ratio of fine- and coarse-grained operation blocks and a heterogeneous floorplan, SGRA offers greater flexibility in the mapping and placement of functional units, thus reducing wasted wiring and improving the critical path delay. We also present an automated design flow for SGRA that is developed by customizing the Verilog-to-Routing (VTR) platform. Experimental results demonstrate that SGRA achieves, on average, a 13% reduction in circuit area over MGRA.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA architecture / Homogeneous array / Technology-mapping using subgraph matching method / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 97, VLD2017-8, pp. 25-30, June 2017.
Paper # VLD2017-8 
Date of Issue 2017-06-12 (CAS, VLD, SIP, MSS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Conference Information
Committee SIP CAS MSS VLD  
Conference Date 2017-06-19 - 2017-06-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Niigata University, Ikarashi Campus 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2017-06-SIP-CAS-MSS-VLD 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation 
Sub Title (in English)  
Keyword(1) FPGA architecture  
Keyword(2) Homogeneous array  
Keyword(3) Technology-mapping using subgraph matching method  
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1st Author's Name Ryosuke Koike  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Takashi Imagawa  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Roberto Yusi Omaki  
3rd Author's Affiliation Synthesis Corporation (Synthesis)
4th Author's Name Hiroyuki Ochi  
4th Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
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Speaker Author-1 
Date Time 2017-06-19 11:00:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # CAS2017-5, VLD2017-8, SIP2017-29, MSS2017-5 
Volume (vol) vol.117 
Number (no) no.96(CAS), no.97(VLD), no.98(SIP), no.99(MSS) 
Page pp.25-30 
#Pages
Date of Issue 2017-06-12 (CAS, VLD, SIP, MSS) 


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