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Paper Abstract and Keywords
Presentation 2017-07-28 16:15
Efficient Message Queuing System Using FPGA NIC
Koya Mitsuzuka, Hiroki Matsutani (Keio Univ.) CPSY2017-38
Abstract (in Japanese) (See Japanese page) 
(in English) Although the FPGA message queuing systems are superior in terms of power efficiency, applicable situation is limited because of its small memory capacity. In order to solve this problem, we propose a message queuing system in which FPGA and CPU work together. Normally, the system by FPGA switch is performed, and message queuing by CPU assists only when memory is insufficient. Owing to this, the proposed system achieves both high power efficiency and large memory capacity.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Message Queuing / Power / / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 153, CPSY2017-38, pp. 215-220, July 2017.
Paper # CPSY2017-38 
Date of Issue 2017-07-19 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2017-38

Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2017-07-26 - 2017-07-28 
Place (in Japanese) (See Japanese page) 
Place (in English) Akita Atorion-Building (Akita) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2017-07-CPSY-DC-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Efficient Message Queuing System Using FPGA NIC 
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Keyword(1) FPGA  
Keyword(2) Message Queuing  
Keyword(3) Power  
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1st Author's Name Koya Mitsuzuka  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Hiroki Matsutani  
2nd Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2017-07-28 16:15:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2017-38 
Volume (vol) vol.117 
Number (no) no.153 
Page pp.215-220 
#Pages 6 
Date of Issue 2017-07-19 (CPSY) 

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