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Paper Abstract and Keywords
Presentation 2017-09-25 14:20
A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization
Tomoya Fujii, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) RECONF2017-26
Abstract (in Japanese) (See Japanese page) 
(in English) For a pre-trained deep convolutional neural network (CNN)
for an embedded system, a high-speed and a low power consumption are required.
In the former of the CNN, it consists of convolutional layers, while
in the latter, it consists of fully connection layers. In the convolutional
layer, the multiply accumulation operation is a bottleneck, while the fully
connection layer, the memory access is a bottleneck. The binarized CNN
has been proposed to realize many multiply accumulation circuit on the
FPGA, thus, the convolutional layer can be done with high-seed operation.
However, even if we apply the binarization to the fully connection layer, the
amount of memory was still bottleneck. In this paper, we propose a neuron pruning technique which eliminates almost part of the weight memory, and apply it to the fully connection layer on the binarized CNN. In that case, since the weight memory is realized by an on-chip memory on the FPGA, it achieves a high speed memory access. To further reduce the memory size, we apply the retraining the CNN after neuron pruning. In this paper,
we propose a sequential-input parallel-output fully connection layer circuit for the binarized fully connection layer, while propose a streaming circuit for the binarized 2D convolutional layer. The experimental results showed that, by the neuron pruning, as for the fully connected layer on the VGG-11 CNN, the number of neurons was reduced by 60.2%, and the amount of memory was reduced by 83% with keeping the 99% baseline recognition accuracy.
Keyword (in Japanese) (See Japanese page) 
(in English) CNN / FPGA / Memory Reduction / Pruning / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 221, RECONF2017-26, pp. 25-30, Sept. 2017.
Paper # RECONF2017-26 
Date of Issue 2017-09-18 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2017-26

Conference Information
Committee RECONF  
Conference Date 2017-09-25 - 2017-09-26 
Place (in Japanese) (See Japanese page) 
Place (in English) DWANGO Co., Ltd. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2017-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization 
Sub Title (in English)  
Keyword(1) CNN  
Keyword(2) FPGA  
Keyword(3) Memory Reduction  
Keyword(4) Pruning  
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1st Author's Name Tomoya Fujii  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Shimpei Sato  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Hiroki Nakahara  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Speaker Author-1 
Date Time 2017-09-25 14:20:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2017-26 
Volume (vol) vol.117 
Number (no) no.221 
Page pp.25-30 
#Pages
Date of Issue 2017-09-18 (RECONF) 


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