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| Presentation | 2017-11-06 14:30 A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.)  VLD2017-35 DC2017-41 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With the miniaturization and high speed of large scale integrated circuits, it has become important to test delay faults. A transition fault that increase delay in a logic gate is one of the delay fault models. Since the detectable delay size of a fault depends on its test pattern, the test quality can not be evaluated sufficiently with fault coverage of the transition faults. As a method to evaluate delay test quality, statistical delay quality model (SDQM) has been proposed. Statistical delay quality level (SDQL) can be improved using tests generated by a commercially available timing aware ATPG tool. At present, methods of seed generation which convert test cubes for detecting faults into seeds are widely used. The care bit rate of the test cubes increases and the encodability of such cubes becomes low when the methods are used with a timing aware ATPG. In this paper, we propose a method of SDQL-aware LFSR seed generation using a time expansion model of an LFSR. We also evaluate the effectiveness of the proposed method by experiments using ITC’99 benchmark circuits. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | BIST / LFSR / Seed Generation / Time Expansion Model / Transition Fault / SDQM / / | |
| Reference Info. | IEICE Tech. Rep., vol. 117, no. 274, DC2017-41, pp. 49-54, Nov. 2017. | |
| Paper # | DC2017-41 | |
| Date of Issue | 2017-10-30 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2017-35 DC2017-41 |
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| Conference Information | |
| Committee | VLD DC CPSY RECONF CPM ICD IE IPSJ-SLDM |
| Conference Date | 2017-11-06 - 2017-11-08 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kumamoto-Kenminkouryukan Parea |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2017 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2017-11-VLD-DC-CPSY-RECONF-CPM-ICD-IE-SLDM-EMB-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST |
| Sub Title (in English) | |
| Keyword(1) | BIST |
| Keyword(2) | LFSR |
| Keyword(3) | Seed Generation |
| Keyword(4) | Time Expansion Model |
| Keyword(5) | Transition Fault |
| Keyword(6) | SDQM |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kyonosuke Watanabe |
| 1st Author's Affiliation | Oita University (Oita Univ.) |
| 2nd Author's Name | Satoshi Ohtake |
| 2nd Author's Affiliation | Oita University (Oita Univ.) |
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| Speaker | Author-1 |
| Date Time | 2017-11-06 14:30:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2017-35, DC2017-41 |
| Volume (vol) | vol.117 |
| Number (no) | no.273(VLD), no.274(DC) |
| Page | pp.49-54 |
| #Pages | 6 |
| Date of Issue | 2017-10-30 (VLD, DC) |
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