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Paper Abstract and Keywords
Presentation 2018-01-18 16:00
Integrated Machine Code Monitor on FPGA
Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.) VLD2017-73 CPSY2017-117 RECONF2017-61
Abstract (in Japanese) (See Japanese page) 
(in English) Machine code monitor is necessary for initial program development stage when implementing a new processor with unique ISA on FPGA. This paper propose a machine code monitor which is written in HDL and implemented with a target processor on FPGA. The proposed monitor provides an optimal configured monitor functions according to verification status of the processor and development situation of programs. Through implementation and evaluation of the proposed monitor on FPGA, it was confirmed that processor design and verification can be advanced in the target environment even in the middle of developing software development tools for the processor.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Hardware description language / ISA / Machine code monitor / Processor / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 379, RECONF2017-61, pp. 65-70, Jan. 2018.
Paper # RECONF2017-61 
Date of Issue 2018-01-11 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-73 CPSY2017-117 RECONF2017-61

Conference Information
Committee IPSJ-ARC VLD CPSY RECONF IPSJ-SLDM  
Conference Date 2018-01-18 - 2018-01-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To RECONF 
Conference Code 2018-01-ARC-VLD-CPSY-RECONF-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Integrated Machine Code Monitor on FPGA 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Hardware description language  
Keyword(3) ISA  
Keyword(4) Machine code monitor  
Keyword(5) Processor  
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Keyword(8)  
1st Author's Name Hiroaki Kaneko  
1st Author's Affiliation Tokyo Denki University (TokyoDenki Univ.)
2nd Author's Name Akinori Kanasugi  
2nd Author's Affiliation Tokyo Denki University (TokyoDenki Univ.)
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Speaker Author-1 
Date Time 2018-01-18 16:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2017-73, CPSY2017-117, RECONF2017-61 
Volume (vol) vol.117 
Number (no) no.377(VLD), no.378(CPSY), no.379(RECONF) 
Page pp.65-70 
#Pages 6 
Date of Issue 2018-01-11 (VLD, CPSY, RECONF) 

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