| Paper Abstract and Keywords |
| Presentation |
2018-01-19 15:20
Examination of reduction technique for radiation noise from the power supply layers in PCB
-- Evaluation by actual measurement -- Kazuki Fueta, shiniti Sasaki (Saga Univ.) EMCJ2017-103 |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Recently, by high-speed switching of transistors in LSI, the radiation noise from the power supply layers in PCB has increased. We have suggested a method attaching resistor to reduce radiation noise. The method is effective for the power supply layers with grid pattern. In this research, the effectiveness of the resistance addition method was confirmed by actually manufacturing the substrate and measuring the radiation noise. As a result of actual measurement, resistance addition method was effective. However, in the relationship between resistance addition pitch and frequency, results different from simulation were obtained. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Printed Circuit Board / Radiation noise / Power supply noise / Resistance attaching method / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 117, no. 384, EMCJ2017-103, pp. 89-92, Jan. 2018. |
| Paper # |
EMCJ2017-103 |
| Date of Issue |
2018-01-11 (EMCJ) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Download PDF |
EMCJ2017-103 |
| Conference Information |
| Committee |
EMCJ |
| Conference Date |
2018-01-18 - 2018-01-19 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Communication, PCB, Information Security, EMC |
| Paper Information |
| Registration To |
EMCJ |
| Conference Code |
2018-01-EMCJ |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Examination of reduction technique for radiation noise from the power supply layers in PCB |
| Sub Title (in English) |
Evaluation by actual measurement |
| Keyword(1) |
Printed Circuit Board |
| Keyword(2) |
Radiation noise |
| Keyword(3) |
Power supply noise |
| Keyword(4) |
Resistance attaching method |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Kazuki Fueta |
| 1st Author's Affiliation |
Saga University (Saga Univ.) |
| 2nd Author's Name |
shiniti Sasaki |
| 2nd Author's Affiliation |
Saga University (Saga Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2018-01-19 15:20:00 |
| Presentation Time |
25 minutes |
| Registration for |
EMCJ |
| Paper # |
EMCJ2017-103 |
| Volume (vol) |
vol.117 |
| Number (no) |
no.384 |
| Page |
pp.89-92 |
| #Pages |
4 |
| Date of Issue |
2018-01-11 (EMCJ) |