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Paper Abstract and Keywords
Presentation 2018-01-27 14:25
A study on FPGA implementation of SAM spiking neural network
Minoru Motoki, Kazunori Matsuo, Hirohito Shintani (NIT, Kumamoto Col.) NC2017-65
Abstract (in Japanese) (See Japanese page) 
(in English) his paper describes a design for FPGA implementation of SAM spiking neural network and experimental results of circuit resource and non-linear function approximation performances. We have already proposed a supervised training algorithm for the SAM neuron model. The algorithm has a characteristic which allows multiplierless structure, therefore, the implementation of the SAM neural network into FPGAs can be achieved as ``on-chip learning''. We confirmed that the model was able to be multiplierless structure by the logic synthesis using Quartus Prime Lite. Moreover, we inspected that circuit scales and performances of the task of 3rd degree polynomial function approximation when varying the number of the hidden neurons. As the result, it was clarified that the number of the logic elements which proportions to the number of the hidden neurons was required. In addition, the SAM network achieved a performance that RMS error was less than 0.025 when the network structure was 5:30:5.
Keyword (in Japanese) (See Japanese page) 
(in English) spiking neural network / SAM neuron model / supervised learning / FPGA / on-chip learning / function approximation / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 417, NC2017-65, pp. 89-94, Jan. 2018.
Paper # NC2017-65 
Date of Issue 2018-01-19 (NC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee MBE NC NLP  
Conference Date 2018-01-26 - 2018-01-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyushu Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) ME, generalImplementation of Neuro Computing,Analysis and Modeling of Human Science, 
Paper Information
Registration To NC 
Conference Code 2018-01-MBE-NC-NLP 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A study on FPGA implementation of SAM spiking neural network 
Sub Title (in English)  
Keyword(1) spiking neural network  
Keyword(2) SAM neuron model  
Keyword(3) supervised learning  
Keyword(4) FPGA  
Keyword(5) on-chip learning  
Keyword(6) function approximation  
Keyword(7)  
Keyword(8)  
1st Author's Name Minoru Motoki  
1st Author's Affiliation National Institute of Technology, Kumamoto College (NIT, Kumamoto Col.)
2nd Author's Name Kazunori Matsuo  
2nd Author's Affiliation National Institute of Technology, Kumamoto College (NIT, Kumamoto Col.)
3rd Author's Name Hirohito Shintani  
3rd Author's Affiliation National Institute of Technology, Kumamoto College (NIT, Kumamoto Col.)
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Speaker Author-1 
Date Time 2018-01-27 14:25:00 
Presentation Time 25 minutes 
Registration for NC 
Paper # NC2017-65 
Volume (vol) vol.117 
Number (no) no.417 
Page pp.89-94 
#Pages
Date of Issue 2018-01-19 (NC) 


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