IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2018-02-20 11:00
Locating Hot Spots with Justification Techniques in a Layout Design
Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80
Abstract (in Japanese) (See Japanese page) 
(in English) In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-speed testing causes excessive IR-drop and delay, resulting in over-testing. In order to avoid over-testing, which directly is related to yield loss, test power reduction and efficient power analysis is required. Since excessive IR-drop does not occur in whole area of LSI, locating an area with high IR-drop is very important. There are two techniques to analyze power such as dynamic one and static one. Dynamic techniques require test vectors and its computational cost is expensive. In this work, we proposed a technique to locate an area with high IR-drop with static technique.
Keyword (in Japanese) (See Japanese page) 
(in English) At-speed testing / test power / over-testing / transition delay test / test generation / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 444, DC2017-80, pp. 19-24, Feb. 2018.
Paper # DC2017-80 
Date of Issue 2018-02-13 (DC) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2017-80

Conference Information
Committee DC  
Conference Date 2018-02-20 - 2018-02-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2018-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Locating Hot Spots with Justification Techniques in a Layout Design 
Sub Title (in English)  
Keyword(1) At-speed testing  
Keyword(2) test power  
Keyword(3) over-testing  
Keyword(4) transition delay test  
Keyword(5) test generation  
1st Author's Name Yudai Kawano  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Kohei Miyase  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
3rd Author's Name Seiji Kajihara  
3rd Author's Affiliation Kyushu Institute of Technology (Kyutech)
4th Author's Name Xiaoqing Wen  
4th Author's Affiliation Kyushu Institute of Technology (Kyutech)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2018-02-20 11:00:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2017-80 
Volume (vol) vol.117 
Number (no) no.444 
Page pp.19-24 
Date of Issue 2018-02-13 (DC) 

[Return to Top Page]

[Return to IEICE Web Page]

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan