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Paper Abstract and Keywords
Presentation 2018-02-28 17:20
Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes
Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103
Abstract (in Japanese) (See Japanese page) 
(in English) The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In this paper, we propose a radiation-hardened technique for stacked transistors. We evaluate their radiation hardness by TCAD simulations. Widening the distance between stacked transistors increase their radiation hardness from TCAD simulations. We fabricate three latches which have different distance between stacked transistors in 65 nm FDSOI process. Experimental results reveal that there is no error in stacked transistors widened the distance from 250 nm to 350 nm. We also evaluate the effect of downscaling on stacked transistors to compare with their radiation hardness in 28 nm and 65 nm FDSOI processes. The experimental results prove that stacked transistors are effective radiation-hardened technique for downscaled processes.
Keyword (in Japanese) (See Japanese page) 
(in English) soft error / flip-flop / FDSOI / heavy ion / TCAD simulation / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 455, VLD2017-103, pp. 85-90, Feb. 2018.
Paper # VLD2017-103 
Date of Issue 2018-02-21 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD HWS  
Conference Date 2018-02-28 - 2018-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2018-02-VLD-HWS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes 
Sub Title (in English)  
Keyword(1) soft error  
Keyword(2) flip-flop  
Keyword(3) FDSOI  
Keyword(4) heavy ion  
Keyword(5) TCAD simulation  
1st Author's Name Haruki Maruoka  
1st Author's Affiliation Kyoto Institute of Technology University (KIT)
2nd Author's Name Kodai Yamada  
2nd Author's Affiliation Kyoto Institute of Technology University (KIT)
3rd Author's Name Mitsunori Ebara  
3rd Author's Affiliation Kyoto Institute of Technology University (KIT)
4th Author's Name Jun Furuta  
4th Author's Affiliation Kyoto Institute of Technology University (KIT)
5th Author's Name Kazutoshi Kobayashi  
5th Author's Affiliation Kyoto Institute of Technology University (KIT)
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Speaker Author-1 
Date Time 2018-02-28 17:20:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2017-103 
Volume (vol) vol.117 
Number (no) no.455 
Page pp.85-90 
Date of Issue 2018-02-21 (VLD) 

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