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| Presentation | 2018-02-28 14:20 Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU)  VLD2017-97 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We develop a loop flattening tool for designing hardware with high level synthesis. When loop pipelining is applied to nested for-loops, the overhead in the number of execution cycles occurs. Loop flattening is one of the ways to reduce this overhead. At least three loop flattening method exists, so it is necessary to manually select the optimal one for a given nested loop. In order to facilitate this selection, we propose an automatic flow of loop flattening. In this paper, we experimentally evaluate the three loop flattening method and derive the criteria to select the best loop flattening method from the three for a given loop nest. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | High-Level Synthesis / Loop Flattening / LLVM / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 117, no. 455, VLD2017-97, pp. 49-54, Feb. 2018. | |
| Paper # | VLD2017-97 | |
| Date of Issue | 2018-02-21 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2017-97 |
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| Conference Information | |
| Committee | VLD HWS |
| Conference Date | 2018-02-28 - 2018-03-02 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2018-02-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | High-Level Synthesis |
| Keyword(2) | Loop Flattening |
| Keyword(3) | LLVM |
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| 1st Author's Name | Daisuke Ishikawa |
| 1st Author's Affiliation | Tokyo City University (TCU) |
| 2nd Author's Name | Kenshu Seto |
| 2nd Author's Affiliation | Tokyo City University (TCU) |
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| Speaker | Author-1 |
| Date Time | 2018-02-28 14:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2017-97 |
| Volume (vol) | vol.117 |
| Number (no) | no.455 |
| Page | pp.49-54 |
| #Pages | 6 |
| Date of Issue | 2018-02-21 (VLD) |
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