Paper Abstract and Keywords |
Presentation |
2018-03-01 16:00
A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit Takuya Okamoto, Ryota Yamamoto, Shinya Honda (Nagoya Univ.) VLD2017-116 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Today, Deep Neural Network (DNN) is utilized in various fields. There is a demand for deep learning in the field of embedded systems. On the other hand, DNN classifier on the system requires memory-saving and real–time property. Therefore, we target to FPGA and configure a classifier for deep learning on FPGA with high-level synthesis (HLS) tool. To satisfy the system requirement, we consider an effective C source code description for high level synthesis. Specifically, our proposed accelerators are following: pipelining, prefetching, packing and caching. Compared to the original implementation, the execution speed by each accelerator was 2.3 times, 2.8 times, 5.7 times, 3.3 times faster, respectively. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / DNN / High Level Synthesis / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 117, no. 455, VLD2017-116, pp. 163-168, Feb. 2018. |
Paper # |
VLD2017-116 |
Date of Issue |
2018-02-21 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2017-116 |
Conference Information |
Committee |
VLD HWS |
Conference Date |
2018-02-28 - 2018-03-02 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Okinawa Seinen Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2018-02-VLD-HWS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit |
Sub Title (in English) |
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FPGA |
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DNN |
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High Level Synthesis |
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1st Author's Name |
Takuya Okamoto |
1st Author's Affiliation |
Nagoya University (Nagoya Univ.) |
2nd Author's Name |
Ryota Yamamoto |
2nd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
3rd Author's Name |
Shinya Honda |
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Nagoya University (Nagoya Univ.) |
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Speaker |
Author-1 |
Date Time |
2018-03-01 16:00:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2017-116 |
Volume (vol) |
vol.117 |
Number (no) |
no.455 |
Page |
pp.163-168 |
#Pages |
6 |
Date of Issue |
2018-02-21 (VLD) |
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