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Paper Abstract and Keywords
Presentation 2018-03-01 13:00
An Evaluation of Graph Reduction Technique for Delay Insertion of General-Synchronous Circuit
Yuki Arai, Shuji Tsukiyama (Chuo Univ.) VLD2017-110
Abstract (in Japanese) (See Japanese page) 
(in English) In general-synchronous framework, the clock signal is distributed to each register in optimal individual timing, so that the clock period can be less than the critical delay of a combinatorial circuit. In order to achieve the minimum clock period, we must increase the shortest delay of a combinatorial circuit optimally. This technique is called delay insertion and several papers have been published. However, due to the process variability, delay values may vary chip-by-chip, and hence we must consider delay insertion in a sort of statistical manner. In such a statistical design approach, if delay insertion techniques are complicated, it may be hard to devise a statistical delay insertion algorithm. Therefore, in this paper, we propose a simple heuristic method for delay insertion and evaluate its performance. This method repeats a graph reduction technique, and operations used in the technique are addition and maximum only, similar to statistical static timing analysis.
Keyword (in Japanese) (See Japanese page) 
(in English) graph reduction technique / minimum clock period / delay insertion / general-synchronous circuit / performance evaluation / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 455, VLD2017-110, pp. 127-132, Feb. 2018.
Paper # VLD2017-110 
Date of Issue 2018-02-21 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-110

Conference Information
Committee VLD HWS  
Conference Date 2018-02-28 - 2018-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2018-02-VLD-HWS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Evaluation of Graph Reduction Technique for Delay Insertion of General-Synchronous Circuit 
Sub Title (in English)  
Keyword(1) graph reduction technique  
Keyword(2) minimum clock period  
Keyword(3) delay insertion  
Keyword(4) general-synchronous circuit  
Keyword(5) performance evaluation  
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1st Author's Name Yuki Arai  
1st Author's Affiliation Chuo University (Chuo Univ.)
2nd Author's Name Shuji Tsukiyama  
2nd Author's Affiliation Chuo University (Chuo Univ.)
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Speaker Author-1 
Date Time 2018-03-01 13:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2017-110 
Volume (vol) vol.117 
Number (no) no.455 
Page pp.127-132 
#Pages
Date of Issue 2018-02-21 (VLD) 


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