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Paper Abstract and Keywords
Presentation 2018-03-02 14:05
PL-PUF Implementation by Improvement of Capturing Timing Control Circuit
Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike (AIST) VLD2017-126
Abstract (in Japanese) (See Japanese page) 
(in English) In this study, we demonstrate the first implementation of a pseudo linear feedback shift register physical unclonable function (PL-PUF) on silicon, and a proposal of the power supply design to obtain fine reproducibility. Unlike SRAM PUFs, a PL-PUF can generate responses without memory cells, and therefore is secure against attacks extracting internal memory values. and implement PL-PUF on 65nm CMOS process. Implemented PL-PUF achieves fine reproducibility ($mu$=1.09-10.52$%$ fractional HD) and uniqueness ($mu$=49.01-49.56$%$, $sigma$=5.38-5.77$%$ class-to-class HD, 0.983-0.941 entropy) on silicon.
Keyword (in Japanese) (See Japanese page) 
(in English) PUF / hardware security / ring oscillator / power supply voltage / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 455, VLD2017-126, pp. 225-229, Feb. 2018.
Paper # VLD2017-126 
Date of Issue 2018-02-21 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2017-126

Conference Information
Committee VLD HWS  
Conference Date 2018-02-28 - 2018-03-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2018-02-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) PL-PUF Implementation by Improvement of Capturing Timing Control Circuit 
Sub Title (in English)  
Keyword(1) PUF  
Keyword(2) hardware security  
Keyword(3) ring oscillator  
Keyword(4) power supply voltage  
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1st Author's Name Yasuhiro Ogasahara  
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
2nd Author's Name Yohei Hori  
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
3rd Author's Name Hanpei Koike  
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology (AIST)
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Speaker Author-1 
Date Time 2018-03-02 14:05:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2017-126 
Volume (vol) vol.117 
Number (no) no.455 
Page pp.225-229 
#Pages 5 
Date of Issue 2018-02-21 (VLD) 

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